System and method for memory hub-based expansion bus

• US 7,370,134 B2
• Filed: 03/07/2007
• Issued: 05/06/2008
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): KNOLL, CLIFFORD H
• Application Number:
  US11/715,517
• Publication Number:
  US 20070168595A1
• Time in Patent Office: 426 Days
• Field of Search: 710/100, 710/300, 710/104, 710/311, 710/5, 710/303, 710/2, 710/305, 710/316, 712/11, 712/15, 712/34, 712/220, 365/63, 365/52, 365/230.01, 361/679, 361/684, 345/418, 370/351, 370/338, 370/423, 370/912, 711/105, 711/119, 711/5, 711/149, 713/400, 709/201, 709/219
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: Y10S 370/912 Packet communications

Abstract

A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Claims

1. A memory system comprising:

a memory hub controller;

a memory bus coupled to the memory hub controller;

a plurality of memory modules, each memory module having a memory hub coupled to a plurality of memory devices and to the memory bus; and

an expansion module having a plurality of local memory devices coupled to a subprocessor, the subprocessor configured to couple the expansion module to at least one memory module in the plurality of memory modules through the memory bus, the subprocessor of the memory module operable to provide memory requests to and receive memory responses from the plurality of local memory devices and the plurality of memory devices of the at least one memory module independent of the memory hub controller.

2. The memory system of claim 1 wherein the subprocessor is coupled to input and output devices through a high-speed input/output bus.

3. The memory system of claim 1 wherein the memory request comprises a command packet that includes identification data for identifying either the at least one memory module or the expansion module to which the memory request is directed.

4. The memory system of claim 3 wherein the command packet includes identification data for identifying a dual in-line memory module.

5. The memory system of claim 4 wherein the memory bus comprises a downstream bus configured to couple the command packet from the memory hub controller to the memory hub of the at least one memory module, and further configured to couple either the command packet or the memory response between the subprocessor of the expansion module and the memory hub;

and

an upstream bus configured to couple the memory response from the memory hub of the at least one memory module to the memory hub controller, and further configured to couple either the command packet or the memory response between the subprocessor of the expansion module and the memory hub.

6. The memory system of claim 5 wherein the memory hub of each memory module comprises:

a local memory bus;

at least one memory controller coupled to the local memory bus;

a first link interface circuit coupled to the downstream bus;

a second link interface circuit coupled to the upstream bus; and

a cross bar switch coupled to the at least one memory controller through the local memory bus and coupled to the first and second link interfaces through a link interface bus, the cross bar switch operable to couple the link interface circuits to each other and to the at least one memory controller.

7. The memory system of claim 1 wherein the subprocessor comprises a graphics controller, the graphics controller operable to store and access graphics data in the plurality of local memory devices, and further operable to store and access graphics data in the plurality of memory devices of the at least one memory module independent of the memory hub controller.

8. The memory system of claim 7 wherein the graphics controller is configured to provide video data to a video terminal through a video bus.

9. A memory system comprising:

a system controller;

a plurality of memory modules in communication with the system controller, each having a memory hub coupled to a plurality of memory devices and coupled to each other through a memory bus; and

a first expansion module coupled to the memory bus, the first expansion module comprising;

a first plurality of memory devices; and

a subprocessor circuit coupled to the memory bus and to the plurality of memory devices, the subprocessor circuit operable to provide memory requests to and receive memory responses from the plurality of memory devices, the plurality of memory modules and the system controller.

10. The memory system of claim 9 wherein the memory bus comprises a memory connector operable to couple the plurality of memory devices together to communicate with the system controller.

11. The memory system of claim 10 wherein the plurality of memory modules comprises a plurality of dual in-line memory modules.

12. The memory system of claim 9 wherein the plurality of memory modules and the first expansion module are series coupled in a point-to-point architecture, wherein each of the memory hubs are coupled to each other and to the system controller through a downstream bus and an upstream bus.

13. The memory system of claim 12 wherein the first expansion module is configured to provide data requests and receive data responses through both the downstream and upstream buses.

14. The memory system of claim 13 wherein the first expansion module is assigned a memory module from the plurality of memory modules, the assigned memory module operable to primarily service data requests by the first expansion module.

15. The memory system of claim 9, further comprising a second expansion module, the second expansion module comprising:

a second plurality of memory devices; and

a graphics controller operable to store and access graphics data in the second plurality of memory devices, and further operable to store and access graphics data in the plurality of memory modules independent of the system controller.

16. The memory system of claim 15 wherein the graphics controller is configured to provide video data to a video terminal through a video bus.

17. The memory system of claim 9 wherein the subprocessor circuit is coupled to input and output devices through a high-speed input/output bus.