Methods and structure for error correction in a processor pipeline
First Claim
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1. A processor having a memory interface comprising:
- a multi-stage pipeline for fetching or reading information from a memory coupled to the processor, the pipeline including;
a read stage to read a unit of information from the memory;
a correction stage to correct a soft error detected in a read unit of information; and
a utilization stage to utilize information in the corrected information.
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Abstract
Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correction stages to correct a soft error using the fetched unit of information and the associated error correcting codes. By extending the pipeline, soft error correction does not stall the pipeline and hence system performance is improved in the face of soft errors from an error correcting memory subsystem.
47 Citations
29 Claims
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1. A processor having a memory interface comprising:
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a multi-stage pipeline for fetching or reading information from a memory coupled to the processor, the pipeline including; a read stage to read a unit of information from the memory; a correction stage to correct a soft error detected in a read unit of information; and a utilization stage to utilize information in the corrected information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for correcting soft errors in a pipelined processor coupled to a memory subsystem, the method comprising:
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reading a unit of information from an attached memory in a read stage of the processor pipeline; correcting a soft error in the read information in a correction stage of the processor pipeline; and utilizing the corrected information in a utilization stage of the processor pipeline. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification