Compressing test responses using a compactor

• US 7,370,254 B2
• Filed: 02/13/2004
• Issued: 05/06/2008
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US10/778,950
• Publication Number:
  US 20040230884A1
• Time in Patent Office: 1,544 Days
• Field of Search: 714/724, 714726-733
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

Claims

1. A method for compressing a test response in an integrated circuit, comprising:

inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

producing at least two intermediate values at least partially determined by the test value via logic;

loading at least a portion of the intermediate values into plural memory elements;

producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.

2. The method of claim 1, further comprising determining whether the test value is the expected test value by analyzing the set of output values.

3. The method of claim 1, further comprising locating a source of an error in the integrated circuit based on the set of output values.

4. The method of claim 1, wherein an unknown test value is input into the logic during a time associated with the observation period, and wherein the set of output values is at least partially unaffected by the unknown test value.

5. The method of claim 1, wherein the set of at least two output values comprises at least two output values that are output simultaneously from different respective memory elements.

6. The method of claim 1, wherein at least two of the memory elements are connected via feedback-free logic.

7. The method of claim 1, wherein the plural memory elements at least partially comprise one or more registers.

8. The method of claim 1, in which the act of producing the at least two output values comprises the act of serially shifting at least some of the intermediate values through the memory elements.

9. The method of claim 1, wherein the observation period is less than one half of the unloading period.

10. The method of claim 1, wherein the observation period is less then one hundredth of the unloading period.

11. A method for testing an integrated circuit, comprising repeating the acts of claim 1 for a plurality of the test values.

12. A method for testing an integrated circuit, wherein the acts of claim 1 are performed simultaneously for multiple different test values, and wherein the logic is configured to eliminate one, two, or odd-numbered error masking.

13. An integrated circuit comprising a compactor configured to perform the method of claim 1.

14. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform a method, the method comprising:

inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

producing at least two intermediate values at least partially determined by the test value via logic;

loading at least a portion of the intermediate values into plural memory elements;

producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.

15. The computer-readable medium of claim 14, wherein the compactor is configured such that when an unknown test value is input into the logic during a time associated with the observation period, the set of output values is at least partially unaffected by the unknown test value.

16. The computer-readable medium of claim 14, wherein the set of at least two output values comprises at least two output values that are output simultaneously from different respective memory elements.

17. The computer-readable medium of claim 14, wherein at least two of the memory elements are connected via feedback-free logic.

18. The computer-readable medium of claim 14, wherein the plural memory elements at least partially comprise one or more registers.

19. The computer-readable medium of claim 14, in which the act of producing the at least two output values comprises the act of serially shifting at least some of the intermediate values through the memory elements.

20. The computer-readable medium of claim 14, wherein the observation period is less than one half of the unloading period.

21. The computer-readable medium of claim 14, wherein the observation period is less then one hundredth of the unloading period.

22. A computer-readable medium storing a design database that includes design information for a compactor configured to perform a method, the method comprising:

inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

producing at least two intermediate values at least partially determined by the test value via logic;

loading at least a portion of the intermediate values into plural memory elements;

producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.

23. The computer-readable medium of claim 22, wherein the compactor is configured such that when an unknown test value is input into the logic during a time associated with the observation period, and wherein the set of output values is at least partially unaffected by the unknown test value.

24. The computer-readable medium of claim 22, wherein the set of at least two output values comprises at least two output values that are output simultaneously from different respective memory elements.

25. The computer-readable medium of claim 22, wherein at least two of the memory elements are connected via feedback-free logic.

26. The computer-readable medium of claim 22, wherein the plural memory elements at least partially comprise one or more registers.

27. The computer-readable medium of claim 22, wherein the simulated act of producing the at least two output values comprises the simulated act of serially shifting at least some of the intermediate values through the memory elements.

28. The computer-readable medium of claim 22, wherein the observation period is less than one half of the unloading period.

29. The computer-readable medium of claim 22, wherein the observation period is less then one hundredth of the unloading period.

30. An apparatus for compressing a test response in an integrated circuit, comprising:

means for inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

means for producing at least two intermediate values at least partially determined by the test value via logic;

means for loading at least a portion of the intermediate values into plural memory elements;

means for producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

means for outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.

31. The apparatus of claim 30, further comprising means for determining whether the test value is the expected test value by analyzing the set of output values.

32. The apparatus of claim 30, further comprising means for locating a source of an error in the integrated circuit based on the set of output values.

33. The apparatus of claim 30, wherein when an unknown test value is input into the logic during a time associated with the observation period, the set of output values is at least partially unaffected by the unknown test value.

34. The apparatus of claim 30, wherein the set of at least two output values comprises at least two output values that are output simultaneously from different respective memory elements.

35. The apparatus of claim 30, wherein at least two of the memory elements are connected via feedback-free logic.

36. The apparatus of claim 30, wherein the plural memory elements at least partially comprise one or more registers.

37. The apparatus of claim 30 in which the means for producing the at least two output values comprises a means for serially shifting at least some of the intermediate values through the memory elements.

38. The apparatus of claim 30, wherein the observation period is less than one half of the unloading period.

39. The apparatus of claim 30, wherein the observation period is less then one hundredth of the unloading period.

40. The apparatus of claim 30, wherein the logic is configured to eliminate one, two, or odd-numbered error masking.

41. An integrated circuit comprising the apparatus of claim 30.

42. A computer-readable medium storing computer-executable instructions for causing a computer system to design the apparatus of claim 30.

43. A computer-readable medium storing a design database that includes design information for the apparatus of claim 30.