Partitioning a large design across multiple devices

• US 7,370,302 B1
• Filed: 04/05/2005
• Issued: 05/06/2008
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Raje, Salil R., Ranjan, Abhishek, Knol, David A.
• Primary Examiner(s): Do; Thuan
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US11/099,887
• Time in Patent Office: 1,127 Days
• Field of Search: 716 7- 11, 716/18, 703/19
• US Class Current: 716/105
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

Claims

1. A method of partitioning a design across a plurality of integrated circuits, wherein the design comprises a plurality of logic hierarchies, wherein each logic hierarchy comprises a hierarchical ordering of logic blocks of the design, said method comprising:

for each of a plurality of integrated circuits, creating a software construct representing a physical area of the integrated circuit;

assigning at least one instance of the design to each software construct, wherein a plurality of instances are assigned to a selected software construct, wherein each of the plurality of instances is from a different one of the plurality of logic hierarchies;

automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances; and

creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

2. The method of claim 1, further comprising:

assigning at least one other instance of the design, from a same logic hierarchy as one of the plurality of instances previously assigned to the selected software construct, to at least one other software construct; and

indicating connectivity between the selected software construct and the at least one other software construct.

3. The method of claim 1, further comprising:

removing at least one instance from the selected software construct; and

selectively removing at least one of an input/output buffer, a port, and a net from the selected software construct according to said removing step.

4. The method of claim 3, wherein at least one other instance, from a same logic hierarchy as one of the plurality of instances, is assigned to at least one other software construct, said method further comprising indicating connectivity between the selected software construct and the at least one other software construct.

5. The method of claim 1, further comprising:

assigning at least one other instance, from a same logic hierarchy as one of the plurality of instances, to at least one other software construct; and

determining a number of connections between the selected software construct and the at least one other software construct.

6. The method of claim 5, further comprising providing a notification if the number of connections between the selected software construct and the at least one other software construct exceeds a threshold determined, at least in part, from at least one of a number of inputs or outputs available on the logic devices associated with the selected software construct and the at least one other software construct.

7. The method of claim 1, said step of creating a software construct further comprising creating at least one additional software construct for at least one of the plurality of integrated circuits.

8. The method of claim 7, wherein the selected software construct and the at least one additional software construct are mutually exclusive from one another.

9. The method of claim 7, wherein the selected software construct and the at least one additional software construct overlap one another.

10. The method of claim 7, wherein the at least one additional software construct is nested within the selected software construct.