Static address mapping

• US 7,370,310 B1
• Filed: 08/08/2005
• Issued: 05/06/2008
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Saini, Milan R., Han, Jibin
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Doan; Nghia M.
• Application Number:
  US11/200,454
• Time in Patent Office: 1,002 Days
• Field of Search: 716/4, 716 16- 18, 711202-209, 711/211, 711/217, 711/218
• US Class Current: 716/128
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated circuit is obtained. The system design includes a processor. At least one predefined circuit block in the design is identified as a peripheral connected to a processor. The at least one predefined circuit block is for instantiation in the configurable logic of the integrated circuit. Assigned to the at least one predefined circuit block is a static address range which is obtained from the static addresses. An address map for the design is generated having the at least one predefined circuit block with the static address range. Thus, for example, independent designers designing separate systems having a same set of peripherals may map to the same static address ranges independent of software system builder tool version, board, or processor used.

Claims

1. A method for generating an address map, comprising:

obtaining predetermined static addresses;

obtaining a system design for implementation in an integrated circuit, the system design including a processor internal to the integrated circuit;

the predetermined static addresses being predetermined independently of the system design;

identifying at least one predefined circuit block in the system design, the at least one predefined circuit block being for instantiating in configurable logic of the integrated circuit for coupling to the processor;

assigning to the at least one predefined circuit block a static address range, the static address range obtained from the predetermined static addresses for the processor to address the at least one predefined circuit block; and

generating the address map for the system design having the at least one predefined circuit block with the static address range.

2. The method according to claim 1, wherein the static address range is assigned according to type and instance of the at least one predefined circuit block.

3. The method according to claim 2, wherein one of the types of buses is a processor local bus.

4. The method according to claim 3, wherein the at least one predefined circuit block is selected from a General Purpose Input/Output interface, a Universal Asynchronous Receiver Transmitter, a Gigabit Ethernet Media Access Controller, an Asynchronous Transfer Mode Controller, a Rapid Input/Output Low Voltage Differential Signaling interface, a Double Data Rate interface, and an External Memory Controller.

5. The method according to claim 1, wherein one of the types of buses is an on-chip processor bus.

6. The method according to claim 5, wherein the at least one predefined circuit block is selected from a General Purpose Input/Output interface, a Hard Wired Internal Configuration Access Port, a Universal Asynchronous Receiver Transmitter, an Inter-Integrated Circuit bus interface, a Serial Peripheral Interface, an Ethernet, an Asynchronous Transfer Mode Controller, an Interrupt Controller, a Microprocessor Debug Module, an External Memory Controller, a System Advanced Configuration Environment, a timer, a Direct Memory Address interface, an analog-to-digital converter, a digital-to-analog converter, a Peripheral Component Interconnect, an on-chip processor bus interface, an on-chip processor bus-to-processor local bus bridge, a JTAG Universal Asynchronous Receiver Transmitter, an on-chip processor bus arbiter, and a High-Level Data Link Controller.

7. The method according to claim 1, wherein one of the types of buses is a device control register bus.

8. The method according to claim 7, wherein the at least one predefined circuit block is selected from an instruction-side on-chip memory controller, a data-side on-chip memory controller, a processor local bus-to-on-chip processor bus bridge, an on-chip processor bus-to-processor local bus bridge, a processor local bus interface, an instruction-side device control register interface, and a device control register interrupt controller.

9. The method according to claim 1, further comprising:

identifying at least one user-defined circuit block in the system design, the at least one user-defined circuit block being for instantiating in the configurable logic of the integrated circuit for coupling to the processor;

assigning to the at least one user-defined circuit block to another static address range, the other static address range obtained from the predetermined static addresses for the processor to address the at least one user-defined circuit block; and

generating the address map for the system design having the at least one user-defined circuit block with the other static address range.

10. The method according to claim 9, wherein the other static address range is assigned according to type and instance of the at least one user-defined circuit block.

11. The method according to claim 10, wherein the integrated circuit is a Field Programmable Gate Array.