Method of manufacturing thin film semiconductor device, thin film semiconductor device, electro-optical device, and electronic apparatus

• US 7,371,624 B2
• Filed: 07/07/2005
• Issued: 05/13/2008
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Intellectuals High-Tech KFT
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Sera, Hiroshi, Eguchi, Tsukasa
• Primary Examiner(s): Graybill; David E
• Application Number:
  US11/175,267
• Publication Number:
  US 20060079035A1
• Time in Patent Office: 1,041 Days
• Field of Search: None
• US Class Current: 438/155
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A method of manufacturing a thin film semiconductor device which includes a thin film transistor having a first semiconductor layer, a gate insulating layer, and a gate electrode which are laminated in this order on a substrate, and a capacitive element having a lower electrode that conductively connects a second semiconductor layer coplanar with the first semiconductor layer, a dielectric layer coplanar with the gate insulating layer, and an upper electrode coplanar with the gate electrode which are laminated in this order on the substrate is provided. The method includes, after simultaneously forming the gate insulating layer and the dielectric layer, and before forming the gate electrode and the upper electrode, introducing dopants into the second semiconductor layer from a first opening of a mask formed on a surface of the substrate to form the lower electrode, and etching a surface of the dielectric layer from the first opening of the mask.

Claims

1. A method of manufacturing a thin film semiconductor device, the thin film semiconductor device including a thin film transistor having a first semiconductor layer, a gate insulating layer, and a gate electrode which are laminated in this order on a substrate, and a capacitive element having a lower electrode that conductively connects a second semiconductor layer coplanar with the first semiconductor layer, a dielectric layer coplanar with the gate insulating layer, and an upper electrode coplanar with the gate electrode which are laminated in this order on the substrate, the method comprising:

after simultaneously forming the gate insulating layer and the dielectric layer, and before forming the gate electrode and the upper electrode,

introducing dopants into the second semiconductor layer from a first opening of a mask formed on a surface of the substrate to form the lower electrode; and

etching a surface of the dielectric layer from the first opening of the mask.

2. The method according to claim 1,

wherein a second opening is formed in the mask to form some or all of source and drain regions in the first semiconductor layer of a thin film transistor having the same conductive type as the dopants of the thin film transistor;

in the introducing of dopants to form the lower electrode, the dopants are introduced to the second semiconductor layer and the first semiconductor layer from the first and second openings; and

in the etching of the dielectric layer, the surface of the dielectric layer and a surface of the gate insulating layer are etched from the first and second openings.

3. The method according to claim 2,

wherein the source and drain regions have lightly doped source and drain regions self-aligned in the gate electrode, and highly doped source and drain regions adjacent to the lightly doped source and drain regions;

and

the second opening is formed in a region where the highly doped source and drain regions are to be formed.

4. The method according to claim 1, wherein the etching of the dielectric layer is performed using an etchant that etches and removes the dielectric layer and the mask, after the introducing of the dopants to form the lower electrode.