Oxide-nitride stack gate dielectric

• US 7,371,637 B2
• Filed: 09/24/2004
• Issued: 05/13/2008
• Est. Priority Date: 09/26/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ramkumar, Krishnaswamy, Narayanan, Sundar
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): DINH, THU HUONG T
• Application Number:
  US10/950,332
• Publication Number:
  US 20050067663A1
• Time in Patent Office: 1,327 Days
• Field of Search: 438/257, 257/E21.411, 257/E21.192, 257/E21.129
• US Class Current: 438/257
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Claims

1. A method of making a semiconductor structure, comprising:

forming an oxide layer, on a substrate, wherein the oxide layer contains less than 2% nitrogen;

forming a silicon nitride layer on the oxide layer;

annealing the layers in NO; and

annealing the layers in ammonia;

wherein the equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

2. The method of claim 1, wherein the oxide layer has a thickness of 6-10 Angstroms.

3. The method of claim 1, wherein the silicon nitride layer has a thickness of 10-30 Angstroms.

4. The method of claim 1, wherein the forming of the oxide layer comprises rinsing the substrate with deionized water containing ozone.

5. The method of claim 1, wherein the forming of the oxide layer comprises steam oxidation.

6. The method of claim 1, wherein the forming of the oxide layer comprises thermally growing the oxide layer with oxygen.

7. The method of claim 1, wherein the forming of the silicon nitride layer comprises depositing the silicon nitride by LPCVD.

8. The method of claim 1, wherein the annealing in NO is carried out at a temperature of 800-900°

C. for 15-30 minutes.

9. The method of claim 1, wherein the annealing in ammonia is carried out by rapid thermal annealing at a temperature of 900°

C. for 0.5-1 minute.

10. The method of claim 1, wherein the annealing in ammonia is carried out in a furnace at a temperature of 900°

C. for 5-10 minutes.

11. The method of claim 1, wherein the semiconductor structure is a gate dielectric.

12. A method of forming a gate dielectric, comprising:

forming an oxide layer, on a substrate, wherein the oxide layer contains less than 2% nitrogen;

forming a silicon nitride layer on the oxide layer; and

annealing the layers in NO and ammonia;

wherein the oxide layer has a thickness of 6-10 Angstroms, and the silicon nitride layer has a thickness of 10-30 Angstroms.