Top layers of metal for high performance IC's
First Claim
Patent Images
1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a metal trace over said passivation layer and over said first region, wherein said metal trace comprises electroplated copper, and wherein said metal trace is connected to said first pad through said first opening.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
47 Citations
24 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate;
multiple devices in and on said silicon substrate;a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, and wherein said metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a metal trace over said passivation layer and over said first region, wherein said metal trace comprises electroplated copper, and wherein said metal trace is connected to said first pad through said first opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, wherein said first pad comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 30 micrometers and greater than that of said passivation layer; and a second metallization structure in said second opening and on said polymer layer, wherein said second metallization structure comprises electroplated copper in said second opening and over said polymer layer, and wherein said second metallization structure is connected to said first pad. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 30 micrometers and greater than that of said passivation layer; a second metallization structure in said second opening and on said polymer layer, wherein said second metallization structure comprises electroplated copper in said second opening and over said polymer layer; and a solder bump over said electroplated copper of said second metallization structure, over said first and second openings and over said first pad, wherein said solder bump is connected to said first pad through said second metallization structure. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification