Vertical gate semiconductor device and method for fabricating the same

• US 7,372,088 B2
• Filed: 12/21/2004
• Issued: 05/13/2008
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mizokuchi, Shuji, Miyata, Satoe
• Primary Examiner(s): Geyer; Scott B.
• Application Number:
  US11/016,713
• Publication Number:
  US 20050161734A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/E27.091, 257/E29.201, 257/E29.257, 257/E29.26
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A source region is formed by performing ion implantation plural times to diffuse an impurity from the upper surface of a semiconductor region toward a region far dawn therefrom and to increase impurity concentration in the vicinity of the upper surface of the semiconductor region, whereby the source region and a gate electrode are overlapped with each other surely. Thus, offset between the gate and the source is prevented and an excellent ohmic contact is formed between a source electrode and the source region.

Claims

1. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein an upper end of said insulating film is located lower than an upper surface of said semiconductor region.

2. The semiconductor device of claim 1, wherein

said drain region includes:

a first conductivity type high concentration drain region; and

a first conductivity type low concentration drain region provided on said high concentration drain region.

3. The semiconductor device of claim 2, wherein

an impurity concentration of said high concentration drain region is over about 1×

10¹⁹ atoms/cm³ and,

an impurity concentration of said low concentration drain region is below about 5×

10¹⁶ atoms/cm³.

4. The semiconductor device of claim 2, wherein said trench is formed so as to reach said low concentration drain region.

5. The semiconductor device of claim 1, further comprising:

a source electrode provided above said second source region.

6. The semiconductor device of claim 5, wherein

said source electrode is provided at a part above said second source region and on a part where said second source region is exposed at the side surface of said trench.

7. The semiconductor device of claim 5, wherein

a silicide film is provided between said second source region and said source electrode.

8. The semiconductor device of claim 5, wherein

a peak of impurity concentration of said second source region appears within a level range of a height of said source electrode provided on the side surface of said trench.

9. The semiconductor device of claim 1, wherein

an upper end of a part where said gate electrode is in contact with said gate insulating film is located upper than a boundary between said first source region and said body region.

10. The semiconductor device of claim 1, wherein

an upper end of said insulating film is located lower than a peak of impurity concentration of said second source region.

11. The semiconductor device of claim 1, wherein

a second conductivity type impurity region in contact with said body region is provided in a region located on respective sides of said first source region and said second source region in said semiconductor region, and

respective side surfaces of said first source region and said second source region are surrounded by said trench and said impurity region.

12. The semiconductor device of claim 1, wherein

a peak of impurity concentration of said first source region is located lower than that of said second source region.

13. The semiconductor device of claim 1, wherein

said second source region has a peak of impurity concentration higher than said first source region.

14. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type source region provided on said body region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provide on at least a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein an upper end of said insulating film is located lower than the upper surface of said semiconductor region, and

an impurity concentration of a part of said source region from the upper end of said insulating film to the upper surface of said semiconductor region is equal to or larger than 1×

10²⁰ atoms/cm³.

15. The semiconductor device of claim 14, wherein

said drain region includes:

a first conductivity type high concentration drain region; and

a first conductivity type low concentration drain region provided on said high concentration drain region.

16. The semiconductor device of claim 15, wherein said trench is formed so as to reach said low concentration drain region.

17. The semiconductor device of claim 14, further comprising:

a source electrode provided above said second source region.

18. The semiconductor device of claim 17, wherein

said source electrode is provided at a part above said source region and on a part where said source region is exposed at the side surface of said trench.

19. The semiconductor device of claim 17, wherein a silicide film is provided between said source region and said source electrode.

20. The semiconductor device of claim 17, wherein

a peak of impurity concentration of said source region appears within a level range of a height of said source electrode provided on the side surface of said trench.

21. The semiconductor device of claim 14, wherein

an upper end of a part where said gate electrode is in contact with said gate insulating film is located upper than a boundary between said source region and said body region.

22. The semiconductor device of claim 14, wherein

the upper end of said insulating film is located lower than a peak of impurity concentration of said source region.

23. The semiconductor device of claim 14, wherein

a second conductivity type impurity region in contact with said body region is provided in a region located on a side of said source region in said semiconductor region, and

a side surface of said source region is surrounded by said trench and said impurity region.

24. The semiconductor device of claim 14, wherein said source region is formed by three or more time ion implantation.

25. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench;

an insulating film covering an upper surface of said gate electrode in said trench; and

a source electrode provided above said second source region,

wherein said source electrode is provided at a part above said second source region and on a part where said second source region is exposed at the side surface of said trench.

26. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper, surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein an upper end of a part where said gate electrode is in contact with said gate insulating film is located upper than a boundary between said first source region and said body region.

27. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein a second conductivity type impurity region in contact with said body region is provided in a region located on respective sides of said first source region and said second source region in said semiconductor region, and

respective side surfaces of said first source region and said second source region are surrounded by said trench and said impurity region.

28. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench; and

an insulating film covering an upper surface of said gate electrode in said trench,

wherein a peak of impurity concentration of said first source region is located lower than that of said second source region.

29. A semiconductor device, comprising:

a semiconductor region;

a first conductivity type drain region provided in a lower part of said semiconductor region;

a second conductivity type body region provided on said drain region in said semiconductor region;

a first conductivity type first source region provided on said body region in said semiconductor region;

a first conductivity type second source region provided on said first source region in said semiconductor region so as to extend to an upper surface of said semiconductor region;

a trench formed in said semiconductor region and reaching said drain region;

a gate insulating film provided at least on a side surface of said trench;

a gate electrode provided on said gate insulating film in said trench;

an insulating film covering an upper surface of said gate electrode in said trench; and

a source electrode provided above said second source region,

wherein a peak of impurity concentration of said second source region appears within a level range of a height of said source electrode provided on the side surface of said trench.