Pipeline ADC with memory effects achieving one cycle absolute over-range recovery
First Claim
1. A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100), the data conversion stage circuit comprising first and second input capacitor networks (110, 112) switchably coupled to receive an input voltage and switchably coupled to an operational amplifier (opamp) (128) for sampling the input voltage and generating a first residue value related to the sampled input voltage during a second clock phase controlled by a second clock signal and a second residue value related to the first residue value during a first clock phase controlled by a first clock signal, the opamp having positive and negative input terminals (136, 137) and positive and negative output terminals (138, 139), the data conversion stage circuit comprising:
- an over-range detection and recovery circuit comprising;
a first switch (S3) connected between the positive and the negative input terminals (136, 137) of the opamp (128), the first switch being controlled by a first control signal and being closed when the first control signal is asserted;
a second switch (S4) connected between the positive and the negative output terminals (138, 139) of the opamp (128), the second switch being controlled by the first control signal and being closed when the first control signal is asserted; and
a logic circuit (150) coupled to receive the first residue value, a high comparison voltage level, and a low comparison voltage level and to generate the first control signal, the logic circuit comparing the first residue value to the high and low comparison voltage levels and asserting the first control signal during the first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level, wherein the high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit, the reference voltage range defining in-range voltage values for the data conversion stage circuit.
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Accused Products
Abstract
A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100) includes an over-range detection and recovery circuit including first and second switches (S3, S4) connected between respective input terminals (136, 137) and output terminals (138, 139) of the opamp (128) and both controlled by a first control signal, and a logic circuit (150) coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.
11 Citations
11 Claims
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1. A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100), the data conversion stage circuit comprising first and second input capacitor networks (110, 112) switchably coupled to receive an input voltage and switchably coupled to an operational amplifier (opamp) (128) for sampling the input voltage and generating a first residue value related to the sampled input voltage during a second clock phase controlled by a second clock signal and a second residue value related to the first residue value during a first clock phase controlled by a first clock signal, the opamp having positive and negative input terminals (136, 137) and positive and negative output terminals (138, 139), the data conversion stage circuit comprising:
an over-range detection and recovery circuit comprising; a first switch (S3) connected between the positive and the negative input terminals (136, 137) of the opamp (128), the first switch being controlled by a first control signal and being closed when the first control signal is asserted; a second switch (S4) connected between the positive and the negative output terminals (138, 139) of the opamp (128), the second switch being controlled by the first control signal and being closed when the first control signal is asserted; and a logic circuit (150) coupled to receive the first residue value, a high comparison voltage level, and a low comparison voltage level and to generate the first control signal, the logic circuit comparing the first residue value to the high and low comparison voltage levels and asserting the first control signal during the first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level, wherein the high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit, the reference voltage range defining in-range voltage values for the data conversion stage circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method in a data conversion stage (104) of an opamp-shared analog-to-digital converter (100), the method comprising:
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sampling an input voltage at a first input capacitor network (110) and generating a second residue value of a sampled first residue value at an operational amplifier (opamp) (128) during a first clock phase controlled by a first clock signal; generating a first residue value of the input voltage at the opamp and sampling the first residue value at a second input capacitor network (112) during a second clock phase controlled by a second clock signal; comparing the first residue value to a high comparison voltage level; comparing the first residue value to a low comparison voltage level, wherein the high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit, the reference voltage range defining in-range voltage values for the data conversion stage circuit; asserting a control signal during the first clock phase when the first residue value is greater than the high comparison voltage level or less than the low comparison voltage level; shorting input terminals of the opamp together in response to the control signal being asserted; and shorting output terminals of the opamp together in response to the control signal being asserted. - View Dependent Claims (10, 11)
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Specification