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Pipeline ADC with memory effects achieving one cycle absolute over-range recovery

  • US 7,372,391 B1
  • Filed: 02/21/2007
  • Issued: 05/13/2008
  • Est. Priority Date: 09/22/2006
  • Status: Active Grant
First Claim
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1. A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100), the data conversion stage circuit comprising first and second input capacitor networks (110, 112) switchably coupled to receive an input voltage and switchably coupled to an operational amplifier (opamp) (128) for sampling the input voltage and generating a first residue value related to the sampled input voltage during a second clock phase controlled by a second clock signal and a second residue value related to the first residue value during a first clock phase controlled by a first clock signal, the opamp having positive and negative input terminals (136, 137) and positive and negative output terminals (138, 139), the data conversion stage circuit comprising:

  • an over-range detection and recovery circuit comprising;

    a first switch (S3) connected between the positive and the negative input terminals (136, 137) of the opamp (128), the first switch being controlled by a first control signal and being closed when the first control signal is asserted;

    a second switch (S4) connected between the positive and the negative output terminals (138, 139) of the opamp (128), the second switch being controlled by the first control signal and being closed when the first control signal is asserted; and

    a logic circuit (150) coupled to receive the first residue value, a high comparison voltage level, and a low comparison voltage level and to generate the first control signal, the logic circuit comparing the first residue value to the high and low comparison voltage levels and asserting the first control signal during the first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level, wherein the high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit, the reference voltage range defining in-range voltage values for the data conversion stage circuit.

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