Architecture and method for NAND flash memory

• US 7,372,715 B2
• Filed: 06/14/2006
• Issued: 05/13/2008
• Est. Priority Date: 06/14/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Han, Jin-Man
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/452,697
• Publication Number:
  US 20070291565A1
• Time in Patent Office: 699 Days
• Field of Search: 365/63, 365/207, 365/208, 365/185.17
• US Class Current: 365/63
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

Claims

1. A memory array, comprising:

an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines; and

a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.

2. The memory array of claim 1, and further comprising:

a non-connected bitline positioned between the first portion of the array and the second portion of the array.

3. The memory array of claim 2, wherein the array comprises one non-connected bitline per page of the array.

4. The memory array of claim 1, wherein the array comprises one non-connected bitline per 64 bitlines.

5. The memory array of claim 1, and further comprising:

an isolation region between the first portion of the array and the second portion of the array.

6. A memory device, comprising:

an array of non-volatile memory cells accessed by bitlines and word lines;

circuitry for control and/or access of the array of non-volatile memory cells; and

a plurality of sense amplifiers, each sense amplifier connected to two bitlines, an even and an odd bitline, each even bitline positioned in a first portion of the array and each odd bitline positioned in a second portion of the array separate from the first portion of the array.

7. The memory device of claim 6, and further comprising:

a non-connected bitline positioned between the first portion of the array and the second portion of the array.

8. The memory device of claim 7, wherein the array comprises one non-connected bitline per page of the array.

9. The memory device of claim 6, wherein the array comprises one non-connected bitline per 64 bitlines.

10. The memory device of claim 6, wherein the array comprises a plurality of pages, each page having 64 bitlines and 32 sense amplifiers, and wherein the odd bitline portion of each array is adjacent to the odd portion of its adjacent array, and wherein the even bitline portion of each array is adjacent to the even portion of its adjacent array.

11. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises;

an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines; and

a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.

12. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises;

an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines; and

a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.

13. An electronic system, comprising:

a processor; and

one or more memory device coupled to the processor, wherein at least one of the memory devices comprises;

an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines; and

a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.

14. A processing system, comprising:

a processor; and

a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells arranged in rows and columns and accessed by bitlines and word lines;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.