Methods of operating magnetic random access memory devices including heat-generating structures

• US 7,372,722 B2
• Filed: 10/31/2005
• Issued: 05/13/2008
• Est. Priority Date: 09/29/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-Hyun, Jeong, Won-Cheol
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/263,521
• Publication Number:
  US 20060062044A1
• Time in Patent Office: 925 Days
• Field of Search: 365/158, 365/171, 365/173, 365/94, 156/235
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence

Abstract

Methods may be provided for operating a magnetic random access memory (MRAM device including a magnetic tunnel junction structure and a heat generating layer. More particularly, a write current may be provided through the magnetic tunnel junction structure and through the heat generating layer, and the write current may have a magnitude sufficient to change a program state of the magnetic tunnel junction structure. Related devices are also discussed.

Claims

1. A method of operating a magnetic random access memory (MRAM) device including a magnetic tunnel junction structure and a heat generating layer, the method comprising:

providing a write current through the magnetic tunnel junction structure and through the heat generating layer wherein the write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure wherein the magnetic tunnel junction structure includes a pinned layer, a free layer, and a tunneling insulating layer between the pinned and free layers, wherein the heat generating layer and the tunneling insulating layer are spaced apart, and wherein the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer are electrically coupled in series so that the write current passes through each of the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer.

2. A method according to claim 1 wherein the heat generating layer comprises at least one of an aluminum oxide (Al₂O₃) layer, an undoped silicon (Si) layer, a silicon carbide (SiC) layer, a silicon oxide (SiO₂) layer, a silicon oxynitride layer (SiON), and/or a chalcogenide layer.

3. A method according to claim 1 wherein the heat generating layer has a thickness of less than about 30 Å

(Angstroms).

4. A method according to claim 1 wherein the magnetic tunnel junction structure and the heat generating layer are electrically connected in series between a bit line and a memory cell access transistor.

5. A method according to claim 4 wherein the heat generating layer is electrically connected between the magnetic tunnel junction structure and the memory cell access transistor.

6. A method according to claim 4 wherein the heat generating layer is electrically connected between the magnetic tunnel junction structure and the bit line.

7. A method according to claim 4 wherein a conductive plug is electrically connected between the magnetic tunnel junction structure and the memory cell access transistor and wherein the magnetic tunnel junction structure and the heat generating layer are electrically connected in series between the conductive plug and the bit line.

8. A method according to claim 7 wherein a contact area between the conductive plug and the heat generating layer is less than a contact area between the heat generating layer and the magnetic tunnel junction structure.

9. A method according to claim 4 wherein a conductive plug is electrically connected between the magnetic tunnel junction structure and the bit line and wherein the magnetic tunnel junction structure and the heat generating layer are electrically connected in series between the conductive plug and the memory cell access transistor.

10. A method according to claim 9 wherein a contact area between the conductive plug and the heat generating layer is less than a contact area between the heat generating layer and the magnetic tunnel junction structure.

11. A method according to claim 1 wherein the write current has a magnitude sufficient to generate heat at the heat generating layer to thereby heat the magnetic tunnel junction structure.

12. A method according to claim 1 further comprising:

providing a read signal through the magnetic tunnel junction structure and through the heat generating layer wherein a magnitude of the read signal is insufficient to change a program state of the magnetic tunnel junction structure; and

determining a program state of the magnetic tunnel junction structure responsive to the read signal.

13. A method according to claim 1 wherein the magnetic random access memory device further includes a bit line and a memory cell access transistor and wherein the magnetic tunnel junction structure and the heat generating layer are electrically connected in series between the memory cell access transistor and the bit line, wherein providing the write current comprises:

turning on the memory cell access transistor; and

applying a bit line write signal to the bit line while turning on the memory cell access transistor to thereby generate the write current through the magnetic tunnel junction structure and the heat generating layer.

14. A method according to claim 1 further comprising a semiconductor substrate wherein the heat generating layer is between the magnetic tunnel junction structure and the substrate.

15. A method according to claim 1 further comprising a semiconductor substrate wherein the magnetic tunnel junction structure is between the heat generating layer and the semiconductor substrate.

16. A method of operating a magnetic random access memory (MRAM) device including a magnetic tunnel junction structure and a heat generating layer, the method comprising:

providing a first write current in a first direction through the magnetic tunnel junction structure and through the heat generating layer wherein the first write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure to a first program state; and

providing a second write current in a second direction through the magnetic tunnel junction structure and through the heat generating layer wherein the second write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure to a second program state, wherein the first and second directions are different and wherein the first and second program states are different.

17. A method according to claim 16 wherein the magnetic tunnel junction structure includes a pinned layer, a free layer, and a tunneling insulating layer between the pinned and free layers, wherein the heat generating layer and the tunneling insulating layer are spaced apart, and wherein the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer are electrically coupled in series so that the first and second write currents pass through each of the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer.

18. A magnetic random access memory (MRAM) device comprising:

a memory cell access transistor on a substrate;

an insulating layer on the memory cell access transistor and on the substrate;

a bit line on the insulating layer such that the insulating layer is between the bit line and the substrate;

a memory element including a magnetic tunnel junction structure and a heat generating layer electrically connected in series between the bit line and a source/drain region of the memory cell access transistor wherein the magnetic tunnel junction structure includes a pinned layer, a free layer, and a tunneling insulating layer between the pinned and free layers, wherein the heat generating layer and the tunneling insulating layer are spaced apart, and wherein the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer are electrically coupled in series; and

a controller electrically connected to the bit line and the memory cell access transistor wherein the controller is configured to provide a write current between the bit line and the source/drain region of the memory cell access transistor through the magnetic tunnel junction structure and through the heat generating layer so that the write current passes through each of the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer wherein the write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure.

19. A magnetic random access memory according to claim 18 wherein the heat generating layer comprises at least one of an aluminum oxide (Al₂O₃) layer, an undoped silicon (Si) layer, a silicon carbide (SiC) layer, a silicon oxide (SiO₂) layer, a silicon oxynitride (SiON) layer, and/or a chalcogenide layer.

20. A magnetic random access memory according to claim 19 wherein the heat generating layer has a thickness of less than about 30 521 (Angstroms).

21. A magnetic random access memory according to claim 18 wherein the heat generating layer is electrically connected between the magnetic tunnel junction structure and the memory cell access transistor.

22. A magnetic random access memory according to claim 18 wherein the heat generating layer is electrically connected between the magnetic tunnel junction structure and the bit line.

23. A magnetic random access memory according to claim 18 further comprising:

a conductive plug electrically connected between the magnetic tunnel junction structure and the memory cell access transistor and wherein the magnetic tunnel junction structure and the heat generating layer are electrically connected in series between the conductive plug and the bit line.

24. A magnetic random access memory according to claim 23 wherein a contact area between the conductive plug and the heat generating layer is less than a contact area between the heat generating layer and the magnetic tunnel junction structure.

25. A magnetic random access memory according to claim 18 further comprising:

a conductive plug electrically connected between the magnetic tunnel junction structure and the bit line and wherein the magnetic tunnel junction structure and the heat gene rating layer are electrically connected in series between the conductive plug and the memory cell access transistor.

26. A magnetic random access memory according to claim 25 wherein a contact area between the conductive plug and the heat generating layer is less than a contact area between the heat generating layer and the magnetic tunnel junction structure.

27. A magnetic random access memory according to claim 18 wherein the write current has a magnitude sufficient to generate heat at the heat generating layer to thereby heat the magnetic tunnel junction structure.

28. A magnetic random access memory according to claim 18 wherein the controller is further configured to:

provide a read signal through the magnetic tunnel junction structure and through the heat generating layer wherein a magnitude of the read signal is insufficient to change a program state of the magnetic tunnel junction structure; and

determine a program state of the magnetic tunnel junction structure responsive to the read signal.

29. A magnetic random access memory according to claim 18 wherein the magnetic tunnel junction structure includes a pinned layer, a free layer, and a tunneling insulating layer between the pinned and free layers, wherein the heat generating layer and the tunneling insulating layer are spaced apart, and wherein the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer are electrically coupled in series so that the first and second write currents pass through each of the pinned layer, the free layer, the tunneling insulating layer, and the heat generating layer.

30. A magnetic random access memory (MRAM) device comprising:

a memory cell access transistor on a substrate;

an insulating layer on the memory cell access transistor and on the substrate;

a bit line on the insulating layer such that the insulating layer is between the bit line and the substrate;

a memory element including a magnetic tunnel junction structure and a heat generating layer electrically connected in series between the bit line and a source/drain region of the memory cell access transistor; and

a controller electrically connected to the bit line and the memory cell access transistor, wherein the controller is configured to;

provide a first write current in a first direction between the bit line and the source/drain region of the memory cell access transistor through the magnetic tunnel junction structure and through the heat generating layer wherein the first write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure to a first program state, and

provide a second write current in a second direction between the bit line and the source/drain region of the memory cell access transistor through the magnetic tunnel junction structure and through the heat generating layer wherein the second write current has a magnitude sufficient to change a program state of the magnetic tunnel junction structure to a second program state, wherein the first and second directions are different and wherein the first and second program states are different.