Apparatus and method for processing a deterministic data flow associated with a wireless communication signal

• US 7,373,121 B1
• Filed: 03/17/2006
• Issued: 05/13/2008
• Est. Priority Date: 12/11/2002
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bahai, Ahmad
• Primary Examiner(s): Feild; Joseph
• Assistant Examiner(s): Nguyen; Huy D
• Application Number:
  US11/378,674
• Time in Patent Office: 788 Days
• Field of Search: 455/466, 455/84, 455/418, 455/453, 455/161.2, 455/164.2, 455/183.2, 455/234.2, 375/219, 375/220, 375/222
• US Class Current: 455/161.2
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The invention is directed to an apparatus, method and system for providing reduced power consumption, fast processing of digitized communication signals and relatively easy reconfiguration for different applications, such as communication protocols/standards. The invention recognizes that the processing of signals associated with different types of communication standards can be recharacterized as deterministic data flows. Also, for each deterministic data flow, several of the same categories of computation are performed in substantially the same manner, albeit in a different order or somewhat differently, that is unique to a particular application. Based on this recharacterization, the invention divides the processing of the deterministic data flow for a communication signal among several Class processors that are separately configurable to optimize their particular category/class of computation in the processing of the signal.

Claims

1. A method for processing a signal, comprising:

receiving the signal from a node and determining at least one data flow associated with the received signal;

determining, based at least on the received signal, at least one of a wireless or wired communication standard associated with the at least one data flow;

configuring a plurality of class processors to perform the processing of the data flow in accordance with the determined communication standard, wherein each class processor is configurable to perform one of a plurality of classes of computation that correspond to the determined communication standard, wherein at least one class processor is reconfigurable to perform another of the plurality of classes of computation based, at least, on another determined communication standard that is determined based, at least, on the received signal; and

providing the data flow to the plurality of class processors for processing, wherein at least one class processor is separately configurable for processing a portion of the data flow at a different speed than at least one of the other class processors that is configurable to perform processing of another portion of the data flow.

2. The method of claim 1, further comprising:

enabling a host processor to receive the processed data flow and enabling the host processor to perform an action based on the content of the processed data flow;

enabling the plurality of class processors to process another data flow that is provided by the host processor to the plurality of class processors for processing; and

transmitting another signal to the node, wherein the generation of the other signal is based on the processed other data flow.

3. The method of claim 1, further comprising

enabling separate clocking of at least one class processor to process its portion of at least one of the data flows associated with a transmitted signal and the received signal, wherein the separate clocking enables asynchronous processing of the data flows associated with at least one of the transmitted signal and the received signal.

4. The method of claim 1, wherein the different speeds are configurable to enable the saving of power in the processing of the data flow.

5. The method of claim 1, wherein the different speeds are configurable to enable reduction in a delay in the processing of the data flow.

6. The method of claim 1, further comprising enabling at least one class processor to be operable at a different voltage level than one or more of the other class processors, wherein the different voltage level is arranged to at least conserve power in the processing of the data flow.

7. The method of claim 1, further comprising enabling at least one bus to control the operation of the plurality of class processors, wherein the at least one bus is operative to configure at least one of a different voltage level and a different clock signal for one or more of the plurality of class processors to at least conserve power in the processing of the data.

8. The method of claim 1, wherein at least one of the plurality of class processors is at least one of manually and automatically configurable to operate with at least one of the determined communication standard.

9. The method of claim 1, further comprising enabling a decoder to store a plurality of pre-decoded instructions for relatively fast processing of the data flow.

10. A processor readable medium that includes executable data for performing actions that process a signal, comprising:

a first component for receiving a signal from a node and providing a data flow associated with the received signal to a plurality of class processors for processing, wherein at least one class processor is separately configurable for processing a portion of the data flow for an application, wherein at least one of the class processors is configurable to perform the processing of the portion of the data flow at a different speed than at least one of the other class processors that is configurable to perform processing of another portion of the data flow, and wherein at least one class processor is reconfigurable from a first configuration for processing a portion of the data flow to a second configuration for processing a portion of another data flow associated with the received signal for another application based, at least, on the received signal;

a second component for enabling a host processor to receive the processed data flow and enabling the host processor to perform an action based on the content of the processed data flow;

a third component for enabling the plurality of class processors to process another data flow that is provided by the host processor to the plurality of class processors for processing; and

a fourth component for transmitting another data signal to the node, wherein the generation of the other data signal is based on the processed other data flow.

11. The processor readable medium of claim 10, further comprising:

(a) a fifth component for converting the received signal into the data flow that is provided to the plurality of class processors; and

(b) a sixth component for converting the processed other data flow into the transmitted signal.

12. The processor readable medium of claim 10, further comprising another component for enabling separate clocking of at least one class processor to process its portion of at least one of the data flows associated with at least one of the transmitted signal and the received signal, wherein the separate clocking enables asynchronous processing of the data flows associated with the at least one of the transmitted signal and the received signal.

13. The processor readable medium of claim 10, wherein the different speeds are configurable to enable the saving of power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

14. The processor readable medium of claim 10, wherein the different speeds are configurable to enable reduction in a delay in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

15. The processor readable medium of claim 10, further comprising another component for enabling at least one class processor to be operable at a different voltage level than one or more of the other class processors, wherein the different voltage level is arranged to at least conserve power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

16. The processor readable medium of claim 10, further comprising another component for enabling at least one bus to control the operation of the plurality of class processors, wherein the at least one bus is operative to configure at least one of a different voltage level and a different clock signal for one or more of the plurality of class processors to at least conserve power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

17. The processor readable medium of claim 10, wherein at least one of the plurality of class processors is separately configurable to operate with at least one of a wireless or wired communication standard.

18. The processor readable medium of claim 17, wherein at least one of the plurality of class processors is at least one of manually and automatically configurable to operate with at least one of the wireless and wired communication standard.

19. The processor readable medium of claim 10, further comprising:

a fifth component for determining at least one of a wireless or wired communication standard associated with the data flows of at least one of the received signal and the transmitted signal; and

a sixth component for configuring the class processors to perform the processing of the data flows in accordance with the determined communication standard.

20. The processor readable medium of claim 10, further comprising another component for enabling a decoder to store a plurality of pre-decoded instructions for relatively fast processing of the data flows associated with at least one of the transmitted signal and the received signal.

21. A system for signal processing, comprising:

a first component for receiving a signal from a node and providing a data flow associated with the received signal to a plurality of class processors for processing, wherein at least one class processor is separately configurable for processing a portion of the data flow for an application, and wherein at least one of the class processors is configurable to perform the processing of the portion of the data flow at a different speed than at least one of the other class processors that is configurable to perform processing of another portion of the data flow;

a host processor that is arranged to receive the processed data flow and perform an action based on the content of the processed data flow, wherein the plurality of class processors are arranged to process another data flow that is provided by the host processor; and

a second component for transmitting another data signal to the node, wherein the generation of the other data signal is based on the processed other data flow.

22. The system of claim 21, further comprising at least one main clock signal that is arranged to synchronize the processing of the data flows between the plurality of class processors.

23. The system of claim 21, further comprising a different clock signal for at least one of the plurality of class processors for process its portion of at least one of the data flows associated with the transmitted signal and the received signal, wherein the different clock signal enables asynchronous processing of the data flows associated with the transmitted signal and the received signal.

24. The system of claim 21, wherein the different speeds are configurable to enable the saving of power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

25. The system of claim 21, wherein the different speeds are configurable to enable reduction in a delay in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

26. The system of claim 21, wherein at least one class processor is operable at a different voltage level than one or more of the other class processors, wherein the different voltage level is arranged to at least conserve power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

27. The system of claim 21, further comprising at least one bus that is arranged for controlling at least a portion of the operation of the plurality of class processors, wherein the at least one bus is operative to configure at least one of a different voltage level and a different clock signal for one or more of the plurality of class processors to at least conserve power in the processing of the data flows associated with at least one of the transmitted signal and the received signal.

28. The system of claim 21, further comprising:

a third component for determining at least one of a wireless or wired communication standard associated with the data flows of at least one of the received signal and the transmitted signal; and

a fourth component for configuring the class processors to perform the processing of the data flows in accordance with the determined communication standard.

29. The system of claim 21, wherein at least one of the plurality of class processors is at least one of manually and automatically configurable to operate with at least one of the wireless and wired communication standard.

30. The system of claim 21, further comprising a decoder arranged to store a plurality of pre-decoded instructions for relatively fast processing of the data flows associated with at least one of the transmitted signal and the received signal.