Method and apparatus for verifying a site-dependent wafer

• US 7,373,216 B1
• Filed: 03/30/2007
• Issued: 05/13/2008
• Est. Priority Date: 03/30/2007
• Status: Expired due to Fees

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Winkler, Mark, Winter, Thomas
• Primary Examiner(s): Picard; Leo
• Assistant Examiner(s): Lee; Douglas S
• Application Number:
  US11/730,283
• Time in Patent Office: 410 Days
• Field of Search: 700/109, 700/110, 700/121, 716/4, 716/12, 716/14, 716/19, 703/2, 438/11
• US Class Current: 700/121
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/31265 Control process by combining history and real time data
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y02P 90/80 Management or planning

Abstract

The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, creating a first set of unverified S-D wafers by performing a first S-D creation procedure, establishing S-D wafer state data for each unverified S-D wafer, establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, establishing first operational states for a plurality of S-D evaluation elements, determining a first number of available evaluation elements, establishing a first S-D transfer sequence, transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems and applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.

Claims

1. A method of verifying a Site-Dependent (S-D) wafer comprising:

receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, wherein the one or more S-D processing elements are coupled to one or more S-D transfer subsystems, each wafer having wafer data associated therewith, wherein the wafer data includes historical and/or real-time data;

creating a first set of unverified S-D wafers by performing a first S-D creation procedure using the one or more S-D processing elements, wherein one or more unverified evaluation features are created at a first number of evaluation sites on each of the unverified S-D wafers;

establishing S-D wafer state data for each unverified S-D wafer, wherein the S-D wafer state data comprises a number of required creation sites and a number of required evaluation sites for each unverified S-D wafer;

establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, the first set of evaluation wafers being evaluated using a first S-D evaluation procedure;

establishing first operational states for a plurality of S-D evaluation elements in one or more subsystems coupled to the one or more S-D transfer subsystems;

determining a first number of available evaluation elements using the first operational states for one or more of the S-D evaluation elements;

establishing a first S-D transfer sequence using the wafer data, the S-D wafer state data, the first number of S-D evaluation wafers, or the first number of available evaluation elements, or any combination thereof;

transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems using the first S-D transfer sequence when the number of S-D evaluation wafers is less than or equal to the first number of available evaluation elements, and

applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.

2. The method of claim 1, further comprising:

determining a number of required evaluation sites for each S-D evaluation wafer using the wafer data, data from the first S-D creation procedure, the S-D wafer state data, or S-D evaluation library creation rules, or any combination thereof;

selecting a first site from the number of required evaluation sites on a first S-D evaluation wafer, wherein the first site has a first unverified evaluation feature associated therewith that was created using the first S-D creation procedure;

obtaining first wafer-verification data from the first site on the first S-D evaluation wafer, wherein the first wafer-verification data comprises first S-D measurement and/or first S-D inspection data;

establishing first verified data for the first site on the first S-D evaluation wafer, wherein the first verified data comprises verified measurement and/or inspection data;

establishing a first confidence value for the first site on the first S-D evaluation wafer using a first wafer-verify difference calculated using the first wafer-verification data and the first verified data;

establishing a first risk factor for the first site on the first S-D evaluation wafer using the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

establishing a first total risk factor for the first S-D evaluation wafer using the first risk factor, the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

identifying the first S-D evaluation wafer as a first verified S-D wafer having the first total risk factor associated therewith, decreasing a number of remaining sites by one, increasing a number of visited sites by one, and identifying the first S-D creation procedure associated with the first S-D evaluation wafer as a first verified S-D procedure, when the first total risk factor is less than or equal to a first wafer-verification limit; and

identifying the first site as a first unverified site having the first risk factor associated therewith, decreasing the number of remaining sites by one, and increasing the number of visited sites by one, when the first total risk factor is greater than the first wafer-verification limit, wherein the first verified S-D evaluation wafer has verified wafer data associated therewith.

3. The method of claim 1, further comprising:

a) selecting a new site from the number of required sites on the first S-D evaluation wafer, wherein the new site has a new unverified evaluation feature associated therewith that was created using the first S-D creation procedure;

b) obtaining new wafer-verification data from the new site on the first S-D evaluation wafer, wherein the new wafer-verification data comprises new S-D measurement and/or new S-D inspection data;

c) establishing new verified data for the new site on the first S-D evaluation wafer, wherein the new verified data comprises new verified measurement and/or inspection data;

d) establishing a new confidence value for the new site on the first S-D evaluation wafer using a new wafer-verify difference calculated using the new wafer-verification data and the new verified data;

e) establishing a new risk factor for the new site on the first S-D evaluation wafer using the new confidence value, the new wafer-verify difference, the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

f) establishing a new total risk factor for the first S-D evaluation wafer using the new risk factor, the new confidence value, the new wafer-verify difference, the first risk factor, the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

g) identifying the first S-D evaluation wafer as a first verified S-D wafer having the new total risk factor associated therewith, decreasing the number of remaining sites by one, increasing the number of visited sites by one, and identifying the first S-D creation procedure associated with the first S-D evaluation wafer as a first verified S-D procedure, when the new total risk factor is less than or equal to a new wafer-verification limit; and

h) identifying the new site as a new unverified site having the new risk factor associated therewith, decreasing the number of remaining sites by one, and increasing the number of visited sites by one, when the first total risk factor is greater than the new wafer-verification limit, wherein the first verified S-D evaluation wafer has new verified wafer data associated therewith;

i) repeating steps a)-h) when the number of required sites is greater than zero; and

j) stopping a S-D library creation process when the number of required sites is equal to zero.

4. The method of claim 1, further comprising:

a1) selecting an additional S-D evaluation wafer;

b1) determining a first number of required sites for the additional S-D evaluation wafer;

c1) selecting an additional site from the first number of required sites on the additional S-D evaluation wafer, wherein the additional site has an additional unverified evaluation feature associated therewith that was created using the first S-D creation procedure;

d1) obtaining additional wafer-verification data from the additional site on the additional S-D evaluation wafer, wherein the additional wafer-verification data comprises additional S-D measurement data and/or S-D inspection data;

e1) establishing additional verified data for the additional site on the additional S-D evaluation wafer, wherein the additional verified data comprises additional verified measurement and/or inspection data;

f1) establishing an additional confidence value for the additional site on the additional S-D evaluation wafer using an additional wafer-verify difference calculated using the additional wafer-verification data and the additional verified data;

g1) establishing an additional risk factor for the additional site on the additional S-D evaluation wafer using the additional confidence value, the additional wafer-verify difference, the new confidence value, the new wafer-verify difference, the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

h1) establishing an additional total risk factor for the additional site on the additional S-D evaluation wafer using the additional risk factor, the additional confidence value, the additional wafer-verify difference, the new risk factor, the new confidence value, the new wafer-verify difference, the first risk factor, the first confidence value, the first wafer-verify difference, or the wafer data, or any combination thereof;

i1) identifying the additional S-D evaluation wafer as an additional verified S-D wafer having the additional total risk factor associated therewith, decreasing the number of remaining sites by one, increasing the number of visited sites by one, and identifying the first S-D creation procedure associated with the additional S-D evaluation wafer as an additional verified S-D procedure, when the additional total risk factor is less than or equal to an additional wafer-verification limit; and

j1) identifying the additional site as an additional unverified site having the additional risk factor associated therewith, decreasing the number of remaining sites by one, and increasing the number of visited sites by one, when the additional total risk factor is greater than the additional wafer-verification limit;

k1) repeating steps a1)-j1) when an additional S-D evaluation wafer is available and the number of required sites on the additional S-D evaluation wafer is greater than zero; and

l1) stopping the S-D library creation process when an additional S-D evaluation wafer is not available or the number of required sites on the additional S-D evaluation wafer is equal to zero.

5. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a difference between the first number of S-D evaluation wafers and the first number of available evaluation elements; and

storing the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the S-D transfer subsystem, wherein each transfer element comprises means for supporting two or more wafers.

6. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a difference between the first number of S-D evaluation wafers and the first number of available evaluation elements; and

delaying the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the S-D transfer subsystem, wherein each transfer element comprises means for supporting two or more wafers.

7. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a difference between the first number of S-D evaluation wafers and the first number of available evaluation elements;

determining updated S-D wafer state data for a first delayed S-D evaluation wafer;

determining updated operational state data for the one or more S-D evaluation elements in a first evaluation subsystem;

determining a first updated transfer sequence for the first delayed S-D evaluation wafer;

identifying one or more newly-available S-D evaluation elements using the updated operational state data;

transferring the first delayed S-D evaluation wafer to a first newly-available S-D evaluation element in the one or more evaluation subsystems using the first updated transfer sequence when a first newly-available S-D evaluation element is available; and

applying a second corrective action when the first newly-available S-D evaluation element is not available.

8. The method of claim 1, wherein the applying a first corrective action comprises stopping a processing, pausing the processing, re-evaluating one or more of the S-D evaluation wafers, re-measuring one or more of the S-D evaluation wafers, re-inspecting one or more of the S-D evaluation wafers, re-working one or more of the S-D evaluation wafers, storing one or more of the S-D evaluation wafers, cleaning one or more of the S-D evaluation wafers, delaying one or more of the S-D evaluation wafers, or stripping one or more of the S-D evaluation wafers, or any combination thereof.

9. The method of claim 7, wherein the applying a second corrective action comprises stopping a processing, pausing the processing, re-evaluating one or more of the S-D evaluation wafers, re-measuring one or more of the S-D evaluation wafers, re-inspecting one or more of the S-D evaluation wafers, re-working one or more of the S-D evaluation wafers, storing one or more of the S-D evaluation wafers, cleaning one or more of the S-D evaluation wafers, delaying one or more of the S-D evaluation wafers, or stripping one or more of the S-D evaluation wafers, or any combination thereof.

10. The method of claim 1, further comprising:

calculating S-D confidence maps for the unverified S-D wafers, a first S-D confidence map including confidence data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers; and

establishing the first set of S-D evaluation wafers using the S-D confidence maps for the unverified S-D wafers.

11. The method of claim 2, further comprising:

calculating S-D confidence maps for the unverified S-D wafers, a first S-D confidence map including confidence data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D confidence map are not within a first confidence limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D confidence map are within the first confidence limit.

12. The method of claim 2, further comprising:

calculating S-D risk assessment maps for the unverified S-D wafers, a first S-D risk assessment map including risk assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are not within a first confidence limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are within the first confidence limit.

13. The method of claim 1, wherein a S-D evaluation library data comprises goodness of fit data, creation rules data, S-D measurement data, S-D inspection data, S-D verification data, S-D mapping data, S-D confidence data, S-D accuracy data, S-D process data, or S-D uniformity data, or any combination thereof.

14. The method of claim 2, wherein the first wafer-verification data includes S-D intensity data, S-D transmission data, S-D absorption data, S-D reflectance data, or S-D diffraction data, or any combination thereof.

15. The method of claim 3, wherein the first verified data is verified using CD-scanning electron microscope (CD-SEM) data, transmission electron microscope (TEM) data, and/or focused ion beam (FIB) data.

16. The method of claim 1, further comprising:

determining a first set of Non-Site-Dependent (N-S-D) wafers to be unverified using a first N-S-D processing sequence, wherein the first N-S-D processing sequence comprises one or more N-S-D procedures; and

transferring the first set of N-S-D wafers to one or more first N-S-D processing elements in one or more first subsystems using the S-D transfer subsystem, the first N-S-D processing sequence being used to determine the one or more first N-S-D processing elements in the one or more first subsystems.

17. The method of claim 1, wherein the processing subsystems comprise at least one of one or more lithography subsystems, one or more scanner subsystems, one or more inspection subsystems, one or more measurement subsystems, one or more evaluation subsystems, one or more etching subsystems, one or more deposition subsystems, one or more thermal processing subsystems, one or more coating subsystems, one or more alignment subsystems, one or more polishing subsystems, one or more storage subsystems, one or more transfer subsystems, one or more cleaning subsystems, one or more rework subsystems, one or more oxidation subsystems, one or more nitridation subsystems, or one or more external subsystems, or any combination thereof.

18. The method of claim 1, wherein the S-D processing elements comprise at least one of one or more S-D lithography-related processing elements, one or more S-D scanner-related processing elements, one or more S-D inspection-related processing elements, one or more S-D measurement-related elements, one or more S-D evaluation-related elements, one or more S-D etch-related processing elements, one or more S-D deposition-related processing elements, one or more S-D thermal processing elements, one or more S-D coating-related processing elements, one or more S-D alignment-related processing elements, one or more S-D polishing-related processing elements, one or more S-D storage-related elements, one or more S-D transfer elements, one or more S-D cleaning-related processing elements, one or more S-D rework-related processing elements, one or more S-D oxidation-related processing elements, one or more S-D nitridation-related processing elements, or one or more S-D external processing elements, or any combination thereof.

19. The method of claim 1, wherein the first S-D creation procedure comprises at least one of one or more S-D lithography-related procedures, one or more S-D scanner-related procedures, one or more S-D inspection-related procedures, one or more S-D measurement-related procedures, one or more S-D evaluation-related procedures, one or more S-D etch-related procedures, one or more S-D deposition-related procedures, one or more S-D thermal processing procedures, one or more S-D coating-related procedures, one or more S-D alignment-related procedures, one or more S-D polishing-related procedures, one or more S-D storage-related procedures, one or more S-D transfer procedures, one or more S-D cleaning-related procedures, one or more S-D rework-related procedures, one or more S-D oxidation-related procedures, one or more S-D nitridation-related procedures, or one or more S-D external procedures, or any combination thereof.

20. The method of claim 2, wherein different confidence levels are established for the first confidence value using different magnitude values for the first wafer-verify difference.

21. The method of claim 1, further comprising:

creating the first set of unverified S-D wafers by depositing a masking layer on a first number of S-D wafers using one or more S-D, lithography-related processing elements, wherein the one or more unverified evaluation features are created at a first number of evaluation sites in the masking layer on each of the unverified S-D wafers.

22. The method of claim 1, further comprising:

creating the first set of unverified S-D wafers by exposing a deposited masking layer on a first number of S-D wafers using one or more S-D scanner-related processing elements, wherein the one or more unverified evaluation features are created at a first number of evaluation sites in the exposed masking layer on each of the unverified S-D wafers.

23. The method of claim 1, further comprising:

creating the first set of unverified S-D wafers by developing an exposed masking layer on a first number of S-D wafers using one or more S-D lithography-related processing elements, wherein one or more unverified evaluation features are created at a first number of evaluation sites in the exposed masking layer on each of the unverified S-D wafers.

24. The method of claim 1, further comprising:

creating the first set of unverified S-D wafers by etching one or more layers on a first number of S-D wafers using one or more S-D lithography-related processing elements, wherein one or more unverified evaluation features are created at a first number of evaluation sites in the one or more etched layers on each of the unverified S-D wafers.

25. The method of claim 1, wherein the first set of S-D wafers are comprise of at least one of semiconductor material, carbon material, dielectric material, glass material, ceramic material, metallic material, oxidized material, mask material, or planarization material, or a combination thereof.

26. The method of claim 2, further comprising:

creating updated wafer data and updated S-D wafer data for the first S-D evaluation wafer; and

storing the updated wafer data and updated S-D wafer data for the first S-D evaluation.

27. The method of claim 4, further comprising:

creating updated wafer data and updated S-D wafer data for the additional S-D evaluation wafer; and

storing the updated wafer data and updated S-D wafer data for the additional S-D evaluation wafer.

28. A method of verifying a Site-Dependent (S-D) wafer comprising:

receiving a S-D wafer and S-D wafer data for the S-D wafer, wherein the S-D wafer comprises a plurality of dies and a number of evaluation sites;

establishing a first S-D evaluation procedure for the S-D wafer, the first S-D evaluation procedure including a first number of evaluation sites;

determining a first processing time for the first S-D evaluation procedure;

comparing the first processing time to a first time limit;

establishing a first updated S-D evaluation procedure for the first S-D wafer, wherein one or more new evaluation sites are added to the first S-D evaluation procedure when the first processing time is less than the first time limit for the first S-D wafer, wherein a number of an evaluation procedure is increased for the first S-D wafer by establishing a first new prioritized S-D evaluation site for the first S-D wafer;

establishing a first updated S-D transfer sequence for the first S-D wafer using a first updated S-D processing sequence;

establishing a second updated S-D processing sequence for the first S-D wafer, wherein one or more S-D evaluation sites are removed from the first S-D processing sequence when the first processing time is greater than the first time limit for the first S-D wafer, wherein the number of evaluation sites is decreased for the first S-D wafer by removing one or more de-prioritized evaluation sites for the first S-D wafer; and

establishing a second updated S-D transfer sequence for the first S-D wafer using the second updated S-D processing sequence.

29. A system for verifying a Site-Dependent (S-D) wafer comprising:

one or more S-D processing elements in one or more processing subsystems configured for receiving a first set of S-D wafers, wherein the one or more S-D processing elements are coupled to one or more S-D transfer subsystems, wherein the one or more S-D processing elements are configured for performing a first S-D creation procedure, wherein one or more unverified evaluation features are created at a first number of evaluation sites on each unverified S-D wafer; and

one or more controllers coupled to the one or more S-D processing elements in the one or more processing subsystems and to the one or more S-D transfer subsystems, wherein at least one controller is configured

to establish S-D wafer state data for each unverified S-D wafer, wherein the S-D wafer state data comprises a number of required creation sites and a number of required evaluation sites for each unverified S-D wafer,

to establish a first set of evaluation wafers comprising a first number of the unverified S-D wafers, the first set of evaluation wafers being evaluated using a first S-D evaluation procedure,

to establish first operational states for a plurality of S-D evaluation elements in one or more subsystems coupled to the one or more S-D transfer subsystems,

to determine a first number of available evaluation elements using the first operational states for one or more of the S-D evaluation elements,

to establish a first S-D transfer sequence using wafer data, the S-D wafer state data, a first number of S-D evaluation wafers, or a first number of available evaluation elements, or any combination thereof, and

to apply a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements, wherein

the one or more S-D transfer subsystems are configured for transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in the one or more evaluation subsystems using the first S-D transfer sequence when the number of S-D evaluation wafers is less than or equal to the first number of available evaluation elements.

30. A method of verifying a Site-Dependent (S-D) wafer comprising:

receiving a first S-D wafer using a S-D transfer system;

transferring the first S-D wafer to a first S-D processing element using the S-D transfer system;

creating one or more unverified S-D wafers, wherein one or more S-D unverified evaluation features are created at one or more sites on a first S-D unverified wafer using a first S-D creation procedure;

determining a first S-D evaluation wafer using the one or more unverified S-D wafers;

transferring the first S-D evaluation wafer to a first S-D evaluation element using the S-D transfer system;

establishing first confidence data for the first S-D evaluation wafer using a first S-D evaluation procedure, wherein a S-D unverified evaluation feature at a first site on the first S-D evaluation wafer is evaluated;

comparing the first confidence data for the first S-D evaluation wafer to first confidence limits;

identifying the first unverified evaluation feature as a high confidence feature having a first level of confidence associated therewith and identifying the first S-D evaluation wafer as a high confidence wafer having the first level of confidence associated therewith, when a first confidence limit is met; and

applying a first corrective action when the first confidence limit is not met.

31. The method of claim 30, wherein the applying a first corrective action comprises:

a) determining a maximum number of evaluation sites on the first S-D evaluation wafer;

b) determining a minimum number of evaluation sites on the first S-D evaluation wafer;

c) creating a first confidence map for the first S-D evaluation wafer;

d) determining a required number of evaluation sites on the first S-D evaluation wafer;

e) selecting a new site on the first S-D evaluation wafer;

f) establishing new confidence data for the first S-D evaluation wafer using a new S-D evaluation procedure, wherein a S-D unverified evaluation feature at the new site on first S-D wafer is evaluated;

g) adding the new site to the first confidence map for the first S-D evaluation wafer;

h) comparing the new confidence data to new first confidence limits for the first S-D evaluation wafer;

i) identifying the S-D unverified evaluation feature at the new site on the first S-D evaluation wafer as a new high confidence feature having a new first level of confidence associated therewith, identifying the first S-D evaluation wafer as a high confidence wafer having the new first level of confidence associated therewith when a new first confidence limit is met;

j) identifying the S-D unverified evaluation feature at the new site on the first S-D evaluation wafer as a new unverified feature having the new confidence data associated therewith, decreasing a number of required sites by one, and increasing a number of visited sites by one, when the new first confidence limit is not met;

k) repeating steps e)-j) when the number of required sites on the first S-D evaluation wafer is greater than zero; and

l) stopping an evaluation of the first S-D evaluation wafer when the number of required sites on the first S-D evaluation wafer is equal to zero.

32. The method of claim 30, wherein the applying the first corrective action comprises:

a1) receiving an additional S-D wafer using the S-D transfer system;

b1) transferring the additional S-D wafer to an additional first S-D processing element using the S-D transfer system;

c1) creating one or more additional unverified S-D wafers, wherein one or more S-D unverified evaluation features are created at one or more sites on each additional S-D unverified wafer using the first S-D creation procedure;

d1) determining an additional S-D evaluation wafer using the additional unverified S-D wafers;

e1) transferring the additional S-D wafer to an additional first S-D evaluation element using the S-D transfer system;

f1) establishing additional first confidence data for the additional S-D evaluation wafer using an additional first S-D evaluation procedure, wherein a S-D unverified evaluation feature at a first site on the additional S-D evaluation wafer is evaluated;

g1) comparing the additional first confidence data to additional first confidence limits for the additional S-D wafer;

h1) identifying the S-D unverified evaluation feature at the first site on the additional S-D evaluation wafer as an additional high confidence feature having an additional first level of confidence associated therewith and identifying the additional S-D evaluation wafer as a high confidence wafer having the additional first level of confidence associated therewith, when an additional first confidence limit is met; and

i1) applying a second corrective action when the additional first confidence limit is not met.

33. The method of claim 32, wherein the applying a second corrective action comprises:

a2) determining a maximum number of evaluation sites on the additional S-D evaluation wafer;

b2) determining a minimum number of evaluation sites on the additional S-D evaluation wafer;

c2) creating a first confidence map for the additional S-D evaluation wafer;

d2) determining a required number of evaluation sites on the additional S-D evaluation wafer;

e2) selecting a new site on the additional S-D evaluation wafer;

f2) establishing new additional confidence data for the additional S-D evaluation wafer using an additional new S-D evaluation procedure, wherein a S-D unverified evaluation feature at the new site on the additional S-D wafer is evaluated;

g2) adding the new site to the first confidence map for the additional S-D evaluation wafer;

h2) comparing the new additional confidence data to new first confidence limits for the additional S-D evaluation wafer;

i2) identifying the S-D unverified evaluation feature at the new site on the additional S-D evaluation wafer as an additional new high confidence feature having an additional new first level of confidence associated therewith, identifying the first S-D evaluation wafer as a high confidence wafer having the additional new level of confidence associated therewith when an additional new confidence limit is met;

j2) identifying the S-D unverified evaluation feature at the new site on the additional S-D evaluation wafer as an additional new unverified feature having the new additional confidence data associated therewith, decreasing a number of required sites by one, and increasing a number of visited sites by one, when the additional new confidence limit is not met;

k2) repeating steps e2)-j2) when the number of required sites on the additional S-D evaluation wafer is greater than zero; and

l2) stopping an evaluation of the additional S-D evaluation wafer when the number of required sites is equal to zero.

34. The method of claim 30, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements; and

storing the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the S-D transfer subsystem, wherein each transfer element comprises means for supporting two or more wafers.

35. The method of claim 30, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements; and

delaying the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the S-D transfer subsystem, wherein each transfer element comprises means for supporting two or more wafers.

36. The method of claim 30, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements;

determining updated S-D wafer state data for a first delayed S-D evaluation wafer;

determining updated operational state data for the one or more S-D evaluation elements in a first evaluation subsystem;

determining a first updated transfer sequence for the first delayed S-D evaluation wafer;

identifying one or more newly-available S-D evaluation elements using the updated operational state data;

transferring the first delayed S-D evaluation wafer to a first newly-available S-D evaluation element in the one or more evaluation subsystems using the first updated transfer sequence when a first newly-available S-D evaluation element is available; and

applying a second corrective action when the first newly-available S-D evaluation element is not available.

37. The method of claim 30 wherein the applying a first corrective action comprises at least one of stopping a processing, pausing the processing, re-evaluating one or more of the S-D evaluation wafers, re-measuring one or more of the S-D evaluation wafers, re-inspecting one or more of the S-D evaluation wafers, re-working one or more of the S-D evaluation wafers, storing one or more of the S-D evaluation wafers, cleaning one or more of the S-D evaluation wafers, delaying one or more of the S-D evaluation wafers, or stripping one or more of the S-D evaluation wafers, or any combination thereof.

38. The method of claim 32, wherein the applying a second corrective action comprises at least one of stopping a processing, pausing the processing, re-evaluating one or more of the S-D evaluation wafers, re-measuring one or more of the S-D evaluation wafers, re-inspecting one or more of the S-D evaluation wafers, re-working one or more of the S-D evaluation wafers, storing one or more of the S-D evaluation wafers, cleaning one or more of the S-D evaluation wafers, delaying one or more of the S-D evaluation wafers, or stripping one or more of the S-D evaluation wafers, or any combination thereof.

39. The method of claim 30, further comprising:

calculating S-D risk assessment maps for the unverified S-D wafers, a first S-D risk assessment map including risk assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers; and

establishing the first set of S-D evaluation wafers using the S-D risk assessment maps for the unverified S-D wafers.

40. The method of claim 31, further comprising:

calculating S-D risk assessment maps for the unverified S-D wafers, a first S-D risk assessment map including risk assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are within a first risk assessment limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are not within the first risk assessment limit.

41. The method of claim 31, further comprising:

calculating S-D damage-assessment maps for the unverified S-D wafers, a first S-D damage-assessment map including damage-assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D damage-assessment map are within a first damage-assessment limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are not within the first damage-assessment limit.

42. The method of claim 30, wherein a S-D evaluation library data comprises goodness of fit data, creation rules data, S-D measurement data, S-D inspection data, S-D verification data, S-D mapping data, S-D confidence data, S-D accuracy data, S-D process data, or S-D uniformity data, or any combination thereof.

43. The method of claim 30, further comprising:

determining a first set of N-S-D wafers to be unverified using a first N-S-D processing sequence, wherein the first N-S-D processing sequence comprises one or more N-S-D procedures; and

transferring the first set of N-S-D wafers to one or more first N-S-D processing elements in one or more first subsystems using the S-D transfer subsystem, the first N-S-D processing sequence being used to determine the one or more first N-S-D processing elements in the one or more first subsystems.

44. The method of claim 30, wherein the first S-D processing element comprises at least one of one or more S-D lithography-related processing elements, one or more S-D scanner-related processing elements, one or more S-D inspection-related processing elements, one or more S-D measurement-related elements, one or more S-D evaluation-related elements, one or more S-D etch-related processing elements, one or more S-D deposition-related processing elements, one or more S-D thermal processing elements, one or more S-D coating-related processing elements, one or more S-D alignment-related processing elements, one or more S-D polishing-related processing elements, one or more S-D storage-related elements, one or more S-D transfer elements, one or more S-D cleaning-related processing elements, one or more S-D rework-related processing elements, one or more S-D oxidation-related processing elements, one or more S-D nitridation-related processing elements, or one or more S-D external processing elements, or any combination thereof.

45. The method of claim 30, wherein the first S-D creation procedure comprises at least one of one or more S-D lithography-related procedures, one or more S-D scanner-related procedures, one or more S-D inspection-related procedures, one or more S-D measurement-related procedures, one or more S-D evaluation-related procedures, one or more S-D etch-related procedures, one or more S-D deposition-related procedures, one or more S-D thermal processing procedures, one or more S-D coating-related procedures, one or more S-D alignment-related procedures, one or more S-D polishing-related procedures, one or more S-D storage-related procedures, one or more S-D transfer procedures, one or more S-D cleaning-related procedures, one or more S-D rework-related procedures, one or more S-D oxidation-related procedures, one or more S-D nitridation-related procedures, or one or more S-D external procedures, or any combination thereof.

46. The method of claim 31, wherein different confidence levels are established for a first confidence value using different magnitude values for a first wafer-verify difference.

47. The method of claim 30, further comprising:

creating the one or more unverified S-D wafers using a mask layer deposition procedure, wherein one or more S-D wafer-verification features are created at one or more sites in a masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.

48. The method of claim 30, further comprising:

creating the one or more unverified S-D wafers using a mask exposure procedure, wherein one or more S-D wafer-verification features are created at one or more sites in an exposed masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is scanner-related.

49. The method of claim 30, further comprising:

creating the one or more unverified S-D wafers using a mask development procedure, wherein one or more S-D wafer-verification features are created at one or more sites in a developed masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.

50. The method of claim 30, further comprising:

creating the one or more unverified S-D wafers using an etching procedure, wherein one or more S-D wafer-verification features are created at one or more sites in one or more etched layers on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.