Multi-channel DMA with shared FIFO
First Claim
1. A data storage area for use in a direct memory access (DMA) circuit comprising:
- a data memory which is shared by a plurality of channels supported by the DMA circuit;
a next read address storage area coupled to the data memory, the next read address storage area stores a next read address indicative of where to read a next data associated with a DMA write over a first currently granted channel; and
a next write address storage area coupled to the data memory, the next write address storage area allocates a plurality of next write addresses, each of the plurality of next write addresses indicative of where to write the next data associated with a DMA read over a second currently granted channel.
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Accused Products
Abstract
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA'"'"'s transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
79 Citations
21 Claims
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1. A data storage area for use in a direct memory access (DMA) circuit comprising:
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a data memory which is shared by a plurality of channels supported by the DMA circuit; a next read address storage area coupled to the data memory, the next read address storage area stores a next read address indicative of where to read a next data associated with a DMA write over a first currently granted channel; and a next write address storage area coupled to the data memory, the next write address storage area allocates a plurality of next write addresses, each of the plurality of next write addresses indicative of where to write the next data associated with a DMA read over a second currently granted channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A direct memory access (DMA) circuit, comprising:
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a read port; a write port; and a unified shared FIFO circuit coupled to the read and write ports, the unified shared FIFO circuit includes; a data memory which is shared amongst a plurality of channels supported by the DMA circuit; and a next write address storage area coupled to the data memory, the next write address storage area allocates a plurality of next write addresses, each of the plurality of next write addresses indicative of where to write a next data of a channel currently being serviced on the read port. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification