Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

• US 7,373,440 B2
• Filed: 08/17/2001
• Issued: 05/13/2008
• Est. Priority Date: 12/17/1997
• Status: Expired due to Fees

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Huppenthal, Jon M., Burton, Lee A., Seeman, Thomas R.
• Primary Examiner(s): Kindred; Alford
• Assistant Examiner(s): Sorrell; Eron J.
• Application Number:
  US09/932,330
• Publication Number:
  US 20020019926A1
• Time in Patent Office: 2,461 Days
• Field of Search: 709/200, 709/225, 709/250, 709/214, 709/215, 710/2, 710/72, 710/65, 710/300, 710/104, 712/11, 712/23, 712/20
• US Class Current: 710/72
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Claims

1. A computer system comprising:

at least one processor;

a controller for coupling said at least one processor to a peripheral bus control block and a memory module bus;

at least one peripheral bus slot coupled to said peripheral bus control block by a peripheral bus;

at least one memory module slot coupled to said memory module bus; and

a processor element associated with said at least one memory module slot for providing a direct data connection between an external device coupled thereto and the memory module slot enabling data exchange directly between the external device and the memory module bus, wherein the processor element exchanges data at memory module bus speeds.

2. The computer system of claim 1 further comprising:

a control connection to said processor element coupled to said peripheral bus for indicating to said at least one processor an arrival of data on said direct data connection to said processor element and memory module bus.

3. The computer system of claim 1 wherein said memory module bus comprises a DIMM bus and wherein said processor element comprises a DIMM physical format for retention within said at least one memory module slot.

4. The computer system of claim 1 wherein said memory module bus comprises a in-line memory module serial interface bus and wherein said processor element comprises a in-line memory module serial interface physical format for retention within said at least one memory module slot.

5. The computer system of claim 1 wherein said external device comprises one of another computer system, switch or network.

6. The computer system of claim 1 wherein said processor element is operative to alter data received from said controller on said memory module bus prior to transmission on said data connection to said external device.

7. The computer system of claim 1 wherein said processor element is operative to alter data received on said data connection from said external device prior to transmission to said controller on said memory module bus.

8. The computer system of claim 1 wherein said processor element comprises:

a field programmable gate array configurable to perform an identified algorithm on an operand provided thereto on said memory module bus and said data connection.

9. A computer system comprising:

at least one processor;

a controller for coupling said at least one processor to a graphics control block and a memory module bus;

at least one graphics bus connection coupled to said graphics control block by a graphics bus;

at least one memory module slot coupled to said memory module bus; and

a processor element associated with said at least one memory module slot for providing a direct data connection between an external device coupled thereto and the memory module slot enabling data exchange directly between the external device and the memory module bus wherein access to the processor element by the controller occurs at memory module bus speeds.

10. The computer system of claim 9 further comprising:

a control connection to said processor element coupled to said graphics bus for indicating to said at least one processor an arrival of data on said direct data connection to said processor element and memory module bus.

11. The computer system of claim 9 wherein said memory module bus comprises a DIMM bus and wherein said processor element comprises a DIMM physical format for retention within said at least one memory module slot.

12. The computer system of claim 9 wherein said memory module bus comprises a in-line memory module serial interface bus and wherein said processor element comprises a in-line memory module serial interface physical format for retention within said at least one memory module slot.

13. The computer system of claim 9 wherein said processor element is operative to alter data received from said controller on said memory module bus prior to transmission on said data connection to said external device.

14. The computer system of claim 9 wherein said processor element is operative to alter data received on said data connection from said external device prior to transmission to said controller on said memory module bus.

15. The computer system of claim 9 wherein said processor element comprises:

a field programmable gate array configurable to perform an identified algorithm on an operand provided thereto on said memory module bus and said data connection.

16. The computer system of claim 9 wherein said at least one processor comprises a plurality of processors.

17. A computer system comprising:

at least one processor;

a controller for coupling said at least one processor to a system maintenance control block and a memory module bus;

at least one system maintenance bus connection coupled to said system maintenance control block by a system maintenance bus;

at least one memory module slot coupled to said memory module bus; and

a processor element associated with said at least one memory module slot for providing a direct data connection between an external device coupled thereto and the memory module slot enabling data exchange directly between the external device and the memory module bus wherein access to the processor element by the controller for data exchange occurs at bus speeds substantially equal to that of the at least one microprocessor.

18. The computer system of claim 17 further comprising:

a control connection to said processor element coupled to said system maintenance bus for indicating to said at least one processor an arrival of data on said direct data connection to said processor element and memory module bus.

19. The computer system of claim 17 wherein said memory module bus comprises a DIMM bus and wherein said processor element comprises a DIMM physical format for retention within said at least one memory module slot.

20. The computer system of claim 17 wherein said memory module bus comprises a in-line memory module serial interface bus and wherein said processor element comprises a in-line memory module serial interface physical format for retention within said at least one memory module slot.

21. The computer system of claim 17 wherein said external device comprises one of another computer system, switch or network.

22. The computer system of claim 17 wherein said processor element is operative to alter data received from said controller on said memory module bus prior to transmission on said data connection to said external device.

23. The computer system of claim 17 wherein said processor element is operative to alter data received on said data connection from said external device prior to transmission to said controller on said memory module bus.

24. The computer system of claim 17 wherein said processor element comprises:

a field programmable gate array configurable to perform an identified algorithm on an operand provided thereto on said memory module bus and said data connection.