Integrated packet bit error rate tester for 10G SERDES

• US 7,373,561 B2
• Filed: 10/09/2003
• Issued: 05/13/2008
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wang, Peiqing, Baumer, Howard A
• Primary Examiner(s): Britt; Cynthia
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US10/681,244
• Publication Number:
  US 20040083077A1
• Time in Patent Office: 1,678 Days
• Field of Search: 714/704, 714/716, 714/712, 714/715, 370/252, 370/389, 702/125
• US Class Current: 714/704
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and is connectable to the channel under test. An interface is used for programming the packet transmit and packet receive circuits. The packet transmit circuit can generate an arbitrary 10G SERDES packet in response to commands from the interface. The packet receive circuit can determine a bit error rate of the channel under test. The second memory can capture received packet data upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, and (c) after an error is detected.

Claims

1. An integrated circuit, comprising:

a substrate;

a plurality of data ports disposed on the substrate; and

an integrated packet bit error rate tester disposed on the substrate for testing a channel coupled to one of the plurality of data ports, including

a packet transmit circuit including a first memory for storing transmit bit error rate test packet data, wherein the packet transmit circuit is coupled to the channel under test;

a packet receive circuit including a second memory for storing received packet compare data and coupled to the channel under test; and

an interface for programming the packet transmit circuit and the packet receive circuit;

wherein said packet transmit circuit and said packet receive circuit are deposited on said substrate;

wherein the packet transmit circuit generates an arbitrary packet pattern in response to a command from the interface; and

wherein the packet receive circuit determines a bit error rate of the channel under test.

2. The integrated circuit of claim 1, wherein the packet transmit circuit includes a first pseudo-random number generator for generating the arbitrary packet pattern.

3. The integrated circuit of claim 2, wherein the packet receive circuit includes a second pseudo-random number generator for generating the same arbitrary packet pattern that is generated by the first pseudo-random number generator.

4. The integrated circuit of claim 1, wherein

the packet transmit circuit includes a byte counter for counting a number of bytes transmitted during bit error rate testing;

the integrated packet bit error rate tester is coupled to the plurality of data ports via a ring bus disposed on the substrate; and

the substrate is a CMOS substrate.

5. The integrated circuit of claim 1, wherein the packet transmit circuit includes a packet counter for counting a number of packets transmitted during bit error rate testing.

6. The integrated circuit of claim 1, wherein the packet receive circuit includes a bit error counter for counting a number of bit errors detected during bit error rate testing.

7. The integrated circuit of claim 1, wherein the packet receive circuit includes a byte error counter for counting a number of bytes with at least one bit in error detected during bit error rate testing.

8. The integrated circuit of claim 1, wherein the packet receive circuit includes a packet error counter for counting a number of packets with at least one byte in error detected during bit error rate testing.

9. The integrated circuit of claim 1, wherein the second memory captures the received packet compare data only after a pre-programmed pattern is detected.

10. The integrated circuit of claim 9, wherein the pre-programmed pattern includes a fixed pattern.

11. The integrated circuit of claim 9, wherein the pre-programmed pattern includes a programmable pattern.

12. The integrated circuit of claim 9, wherein the pre-programmed pattern includes a cyclic redundancy cheek pattern.

13. The integrated circuit of claim 1, wherein the arbitrary packet pattern is received from an external random access memory.

14. The integrated circuit of claim 1, wherein the arbitrary packet pattern can be loaded into a random access memory for bit error rate testing.

15. The integrated circuit of claim 1, wherein the second memory captures the received packet compare data only after a pre-programmed pattern is lost.

16. The integrated circuit of claim 1, wherein the second memory captures the received packet compare data only after an error is detected.

17. The integrated circuit of claim 1, wherein the second memory captures the received packet compare data continuously.

18. The integrated circuit of claim 1, further including a finite state machine for controlling capture of the received packet compare data.

19. The integrated circuit of claim 1, wherein the packet receive circuit includes a byte counter for counting a total number of bytes received.

20. The integrated circuit of claim 1, wherein the packet receive circuit includes a packet counter for counting a total number of packets received.

21. The integrated circuit of claim 1, wherein the packet transmit circuit includes a byte counter for counting a total number of bytes transmitted.

22. The integrated circuit of claim 1, wherein the packet transmit circuit includes a packet counter for counting a total number of packets transmitted.

23. The integrated circuit of claim 1, wherein the arbitrary packet pattern is a ten gigahertz serializer/deserializer packet.

24. An integrated circuit, comprising:

a substrate;

a plurality of data ports disposed on the substrate; and

an integrated packet bit error rate tester disposed on the substrate for testing a channel coupled to one of the plurality of data ports, including

a packet transmit circuit including a first memory for storing transmit bit error rate test packet data, wherein the packet transmit circuit is coupled to the channel under test;

a packet receive circuit including a second memory for capturing received packet compare data from the channel under test; and

an interface for programming the packet transmit circuit and the packet receive circuit;

wherein said packet transmit circuit and said packet receive circuit are deposited on said substrate;

wherein the packet transmit circuit generates an arbitrary serializer/deserializer (SERDES) packet pattern in response to a command from the interface; and

wherein the packet receive circuit determines a bit error rate of the channel under test based on the transmit packet data compared to the receive packet data.

25. The integrated circuit of claim 24, wherein the packet receive circuit includes a byte counter for counting a total number of bytes received and the second memory is configured to capture a received data packet after a pre-programmed pattern is detected.

26. The integrated circuit of claim 24, wherein the packet receive circuit includes a packet counter for counting a total number of packets received.

27. The integrated circuit of claim 24, wherein the packet transmit circuit includes a byte counter for counting a total number of bytes transmitted.

28. The integrated circuit of claim 24, wherein the packet transmit circuit includes a packet counter for counting a total number of packets transmitted.

29. The integrated circuit of claim 24, wherein the packet transmit circuit includes a first pseudo-random number generator for generating the arbitrary SERDES packet pattern.

30. The integrated circuit of claim 29, wherein the packet receive circuit includes a second pseudo-random number generator for generating the same arbitrary SERDES packet pattern that is generated by the first pseudo-random number generator.

31. The integrated circuit of claim 29, wherein the second memory captures the received packet data only after a pre-programmed pattern is detected.

32. The integrated circuit of claim 31, wherein the pre-programmed pattern includes a fixed pattern.

33. The integrated circuit of claim 31, wherein the pre-programmed pattern includes a programmable pattern.

34. The integrated circuit of claim 31, wherein the pre-programmed pattern includes a cyclic redundancy check pattern.

35. The integrated circuit of claim 24, wherein the second memory captures the received packet data only after a pre-programmed pattern is lost.

36. The integrated circuit of claim 24, wherein the second memory captures the received packet data only after an error is detected.

37. The integrated circuit of claim 24, wherein the second memory captures the received packet data continuously.

38. A method of testing a bit error rate of a channel coupled to a transmitter memory that is part of an integrated circuit deposited on a substrate and to a receiver that is part of the integrated circuit deposited on the substrate, comprising:

generating a test packet including an arbitrary marker pattern;

loading the test packet into the transmitter memory in the integrated circuit;

transmitting the test packet from the transmitter memory over the channel;

capturing a received test packet from the channel coupled to the integrated circuit; and

determining the bit error rate of the channel based on the received test packet.

39. The method of claim 38, further including generating an arbitrary ten gigahertz serializer/deserializer (10G SERDES) packet pattern.

40. The method of claim 39, further including generating the arbitrary 10G SERDES packet pattern using a first pseudo-random number generator.

41. The method of claim 39, further including programming the arbitrary 10G SERDES packet pattern through a management data input/output interface.

42. The method of claim 39, further including generating the same arbitrary 10G SERDES packet pattern using a second pseudo-random number generator as the 10G SERDES packet pattern generated by the first pseudo-random number generator.

43. The method of claim 38, further including counting a number of bytes received during the bit error rate testing.

44. The method of claim 38, further including counting a number of packets received during the bit error rate testing.

45. The method of claim 38, further including counting a number of bit errors detected during the bit error rate testing.

46. The method of claim 38, further including counting a number of bytes with errors detected during the bit error rate testing.

47. The method of claim 38, further including counting a number of packets with a byte in error detected during the bit error rate testing.

48. The method of claim 38, further including determining a bit error rate of the channel under test.

49. The method of claim 38, further including counting a number of packets transmitted over the channel.

50. The method of claim 38, further including counting a number of number of bytes transmitted over the channel.