Constraint-driven test generation for programmable logic device integrated circuits

• US 7,373,621 B1
• Filed: 02/01/2005
• Issued: 05/13/2008
• Est. Priority Date: 02/01/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Dastidar, Jayabrata Ghosh
• Primary Examiner(s): Dinh; Paul
• Assistant Examiner(s): NGUYEN, NHA T
• Application Number:
  US11/048,356
• Time in Patent Office: 1,197 Days
• Field of Search: 714725-727, 714/4, 714/5, 714/6, 714/7, 714/16, 716 1- 18
• US Class Current: 714/726
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

A programmable logic device test generation tool is provided that produces test configuration data and test vectors for testing programmable logic device integrated circuits. A graph generation tool converts a netlist or other circuit description of a programmable logic device integrated circuit into a graph having nodes and edges. A timing analysis tool may be used to help produce test constraints. Based on the test constraints, an automatic test generator processes the graph to produce the test configuration data and test vectors. In processing the graph with the automatic test generator, the graph may be divided into multiple testable subgraphs. Each subgraph may be processed using an iterative approach in which a cost function threshold is adjusted in a number of steps until a target test coverage is obtained or processing saturates.

Claims

1. A method for using a programmable logic device test generation tool to generate test configuration data and test vectors for testing a programmable logic device integrated circuit, comprising:

generating a graph of the programmable logic device integrated circuit with the programmable logic device test generation tool;

using the programmable logic device test generation tool to automatically extract multiple testable subgraphs from the graph in separate processing sessions;

processing each extracted testable subgraph in a separate processing session with the programmable logic device test generation tool to produce a corresponding set of test configuration data and test vectors for testing the programmable logic device, wherein the graph and the extracted testable subgraphs contain nodes and edges and wherein the edges represent programmable connections in the programmable logic device integrated circuit; and

during each procession session, using a cost function to determine which portion of the extracted testable subgraph is to be processed, wherein using the cost function comprises incrementing a cost function threshold in successive processing iterations to selectively increase the portion of the extracted testable subgraph that is processed.

2. The method defined in claim 1, further comprising:

during each processing session, iteratively processing successively larger portions of the extracted testable subgraph by successively increasing how many of the edges may be included in test paths in the extracted testable subgraph.

3. The method defined in claim 1 wherein at least some of the nodes represent logic elements, the method further comprising:

using the programmable logic device test generation tool to identify at least some test paths in the testable subgraphs that start and end at the logic elements.

4. The method defined in claim 1 wherein at least some of the nodes represent input-output pins, the method further comprising:

using the programmable logic device test generation tool to identify at least some test paths in the testable subgraphs that start or end at the input-output pins.

5. The method defined in claim 1 wherein the programmable logic device test generation tool comprises a graph generation tool and wherein generating the graph comprises using the graph generation tool to generate the graph from a circuit description of the programmable logic device integrated circuit.

6. The method defined in claim 1 wherein the programmable logic device test generation tool comprises an automatic test generator and wherein using the programmable logic device test generation tool to extract the testable subgraphs comprises using the automatic test generator to process the graph to extract the multiple subgraphs.

7. The method defined in claim 1 wherein the programmable logic device test generation tool comprises an automatic test generator and wherein using the programmable logic device test generation tool to extract the testable subgraphs comprises using the automatic test generator to extract the testable subgraphs by applying a different set of test constraints to the graph for each of the testable subgraphs.

8. The method defined in claim 1 wherein the programmable logic device includes programmable elements that are loaded with the test configuration data during testing, wherein at least some of the nodes represent input/output pins, and wherein the edges represent programmable connections that are controlled by signals from the programmable elements, the method further comprising:

during each processing session, iteratively processing successively larger portions of the extracted testable subgraph by successively extracting increasingly large portions of the extracted testable subgraph by increasing how many edges are included in test paths in the extracted testable subgraph.

9. The method defined in claim 1 further comprising:

providing test constraints; and

using the test constraints in extracting the testable subgraphs.

10. The method defined in claim 9 further comprising using a timing analysis tool to compute at least some of the test constraints.

11. The method defined in claim 9 wherein the test constraints include constraints limiting which edges are available to test, the method further comprising:

using the test constraints limiting which edges are available to test in extracting the testable subgraphs.

12. The method defined in claim 9 wherein at least some of the nodes represent I/O pins and wherein the test constraints include constraints limiting which I/O pins are available to test, the method further comprising:

using the test constraints limiting which I/O pins are available to test in extracting the testable subgraphs.

13. The method defined in claim 1 wherein using the programmable logic device test generation tool to automatically extract the multiple testable subgraphs from the graph G comprises using the cost function to produce test constraints used in extracting the testable subgraphs.

14. A method for testing a programmable logic device integrated circuit, comprising:

using a programmable logic device test generation tool to generate a graph G from a circuit description of the programmable logic device integrated circuit;

using the programmable logic device test generation tool to automatically extract multiple testable subgraphs from the graph G, wherein the graph G and the multiple testable subgraphs include nodes and edges;

processing each extracted testable subgraph in a separate processing session with the programmable logic device test generation tool to produce a corresponding set of test configuration data and test vectors for testing the programmable logic device;

during the processing of each extracted testable subgraph, using a cost function in the programmable logic device test generation tool to determine which portion of the extracted testable subgraph to process, wherein using the cost function to determine which portion of the extracted testable subgraph to process comprises using the programmable logic device test generation tool to automatically extract multiple subsets from the extracted subgraph based on an incrementing hop number index that indicates how many graph edges are permitted in test paths in each subset;

providing the test configuration data and test vectors from the programmable logic device test generation tool to a tester; and

using the tester to load the test configuration data into the programmable logic device integrated circuit, apply the test vectors, and monitor resulting signals from the programmable logic device integrated circuit.

15. The method defined in claim 14 wherein using the programmable logic device test generation tool to automatically extract multiple testable subgraphs from the graph G comprises:

selecting different sets of test constraints with the programmable logic device test generation tool; and

applying each different set of test constraints to the graph G to extract a corresponding one of the multiple testable subgraphs.

16. The method defined in claim 14 wherein using the tester to monitor the resulting signals from the programmable logic device integrated circuit comprises using a scan chain on the programmable logic device integrated circuit to capture the resulting signals.

17. The method defined in claim 14 wherein using the tester to apply the test vectors to the programmable logic device integrated circuit comprises applying at least some of the test vectors using input/output pins on the programmable logic device integrated circuit, wherein at least one of the extracted testable subgraphs includes nodes representing the input/output pins.

18. The method defined in claim 14 wherein using the tester to apply the test vectors to the programmable logic device integrated circuit comprises applying at least some of the test vectors using programmable logic device logic elements on the programmable integrated circuit, wherein at least one of the extracted testable subgraphs includes nodes representing the programmable logic device logic elements.

19. The method defined in claim 14 further comprising using a target test coverage value in determining when each extracted testable subgraph has been processed sufficiently by the programmable logic device test generation tool.

20. The method defined in claim 14 further comprising using a saturation threshold in determining when progress has saturated when incrementing the hop number index during processing of each extracted testable subgraph with the programmable logic device test generation tool.

21. The method defined in claim 14 further comprising ending processing of a given one of the extracted testable subgraphs and beginning processing of another of the extracted testable subgraphs with the programmable logic device test generation tool when it is determined that a target test coverage has been achieved or that processing of the given one of the extracted testable subgraphs has saturated as the hop number index is incremented.

22. Software on a computer-readable storage medium for execution on computing equipment for generating test configuration data and test vectors for testing a programmable logic device integrated circuit, comprising:

code for generating a graph of the programmable logic device integrated circuit;

code for automatically extracting multiple testable subgraphs from the graph in separate processing sessions;

code for processing each extracted testable subgraph in a separate processing session to produce a corresponding set of test configuration data and test vectors for testing the programmable logic device;

code for automatically extracting a portion of each testable subgraph using a cost function; and

code for automatically incrementing a cost function threshold in successive processing iterations of each processing session to selectively increase the portion of the extracted testable subgraph that is extracted.