Method of forming a conductive via through a wafer

• US 7,375,009 B2
• Filed: 08/28/2002
• Issued: 05/20/2008
• Est. Priority Date: 06/14/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Neo, Yong Loo, Boon, Suan Jeung, Chua, Swee Kwang, Chia, Yong Poo
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US10/232,267
• Publication Number:
  US 20030232488A1
• Time in Patent Office: 2,092 Days
• Field of Search: 438/42, 438/113, 438/460, 438/462, 438/667
• US Class Current: 438/460
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures

Abstract

Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Claims

1. A method of creating vias through a wafer, comprising:

sawing into a fabrication side of the wafer;

sawing into a backside of the wafer to form a number of trenches so that the sawing on the fabrication side and the number of trenches cross each other to form the vias;

forming bonding pads by metalization of a nonmasked area of the wafer; and

conductively connecting the vias to a number of bonding pads formed in single lines, a single line of the bonding pads being formed parallel to and equal distant between two sawings on the fabrication side, and wherein the number of trenches is less than the number of bonding pads.

2. The method of claim 1, wherein sawing into the fabrication side includes sawing about half the thickness of the wafer.

3. The method of claim 1, wherein sawing into the fabrication side includes sawing through over about half the thickness of the wafer.

4. The method of claim 1, wherein sawing into the fabrication side includes sawing about three-quarters the thickness of the wafer.

5. The method of claim 1, wherein sawing the fabrication side includes sawing in saw streets in the wafer.

6. A method of creating a via through a wafer, comprising:

sawing into a fabrication side of the wafer using a saw blade;

flipping the wafer;

sawing into a backside of the wafer using the saw blade to form a number of trenches, so that the sawing on the fabrication side and sawing on the backside cross each other to form vias; and

conductively connecting the vias to a number of bonding pads formed in single lines, wherein the bonding pads are formed by metalization of a nonmasked area of the wafer, a single line of the bonding pads being formed parallel to and equal distant between two sawings on the fabrication side, and wherein the number of trenches is less than the number of bonding pads.

7. The method of claim 6, wherein sawing into the fabrication side includes sawing about three-quarters the thickness of the wafer.

8. The method of claim 6, wherein sawing the fabrication side includes sawing in saw streets in the wafer.

9. A method of creating vias through a substrate, comprising:

sawing into a fabrication side of the substrate;

sawing into a backside of the substrate to form a number of trenches so that the sawing on the fabrication side and the number of trenches cross each other to form the vias;

forming bonding pads by metalization of a nonmasked area of the wafer; and

conductively connecting the vias to a number of bonding pads, the bonding pads formed in single lines, a single line of the bonding pads being formed parallel to and equal distant between two sawings on the fabrication side, and wherein the number of trenches is less than the number of bonding pads.

10. The method of claim 9, wherein sawing into the fabrication side includes sawing about half the thickness of the substrate.

11. The method of claim 9, wherein sawing into the fabrication side includes sawing through over about half the thickness of the substrate.

12. The method of claim 9, wherein sawing into the fabrication side includes sawing about three-quarters the thickness of the substrate.

13. The method of claim 9, wherein sawing the fabrication side includes sawing in saw streets in the substrate.

14. A method of creating a via through a substrate, comprising:

metalizing a nonmasked area of the wafer to form bonding pads;

sawing into a fabrication side of the substrate using a saw blade;

flipping the substrate;

sawing into a backside of the substrate using the saw blade to form a number of trenches, so that saw paths on the fabrication side and the trenches on the backside cross each other to form vias; and

conductively connecting the vias to a number of bonding pads formed in single lines, a single line of the bonding pads being formed parallel to and equal distant between two sawings on the fabrication side, and wherein the number of trenches is less than the number of bonding pads.

15. The method of claim 14, wherein sawing into the fabrication side includes sawing about three-quarters the thickness of the substrate.

16. The method of claim 14, wherein sawing the fabrication side includes sawing in saw streets in the substrate.

17. An integrated circuit fabrication method, comprising:

forming an integrated circuit on a first fabrication side of a substrate;

mechanically trenching the first side of the substrate to form more than one first trench; and

mechanically trenching a second back side of the substrate to form at least one second trench that crosses the first trench at an intersection, whereby the intersection forms a via from the first side to the second side; and

conductively connecting the via is to a number of bonding pads on the substrate, wherein the bonding pads are formed by metalization of a nonmasked area of the wafer, the bonding pads formed in single lines, a single line of the bonding pads being formed equal distant between and parallel to two first trenches, and wherein the number of second trenches is less than the number of bonding pads.

18. The method of claim 17, further comprising filling the via with a conductor.

19. The method of claim 18, further comprising connecting the conductor to the integrated circuit.

20. The method of claim 17, wherein mechanically trenching the first side includes sawing the substrate.

21. The method of claim 20, wherein sawing includes sawing in saw streets intermediate a plurality of integrated circuits in the substrate.

22. The method of claim 17, wherein mechanically trenching the second side of the substrate includes sawing orthogonally to the first trench.

23. The method of claim 17, wherein mechanically trenching the second side of the substrate includes sawing the substrate beneath the integrated circuit.

24. A method for forming through holes in a substrate, comprising:

forming more than one first trench on a fabrication side of a substrate, each trench in a saw street of a substrate;

forming a plurality of second trenches in a backside of a substrate so that the second trenches intersect the first trenches to form a plurality of through holes; and

conductively connecting the through holes to a number of bonding pads, wherein the bonding pads are formed by metalization of a nonmasked area of the wafer, the bonding pads formed in single lines, a single line of bonding pads formed parallel to and equal distant between two first trenches, and wherein the number of second trenches is less than the number of bonding pads.

25. The method of claim 24, wherein forming the plurality of second trenches includes forming the plurality of second trenches beneath the active area of the substrate.

26. The method of claim 25, wherein forming the plurality of through holes includes forming through vias at the through holes.

27. The method of claim 25, wherein forming the plurality of second trenches includes forming N plurality of second trenches that is equal to half a number of bond pads on the substrate.

28. The method of claim 27, wherein forming a plurality of second trenches includes inserting a conductor at each intersection of the first trench and the plurality of second trenches.

29. The method of claim 28, wherein inserting a conductor includes forming a trace that connects a bond pad with at least one of the conductors in the intersection.

30. A method of fabricating an integrated circuit device, comprising:

providing a substrate that includes at least one integrated circuit device;

forming more than one first trench in a first direction on a fabrication side of the substrate;

forming a second trench in a second direction on a backside of the substrate so that the second trench crosses the first trench to form a through via in the substrate from the first side to the second side; and

conductively connecting the through via to a number of bond pads, wherein the bonding pads are formed by metalization of a nonmasked area of the wafer, the bonding pads formed on the first side in single lines, a single line of the bonding pads being formed parallel to and equal distant between two first trenches, wherein the number of bond pads is greater than the number of second trenches; and

inserting a conductor in the through via to form an electrical connection on both the first side and the second side.

31. The method of claim 30, wherein providing the substrate includes forming a plurality of integrated circuits on a wafer intermediate saw streets.

32. The method of claim 31, wherein providing the substrate includes forming saw streets in the first direction, and wherein forming the first trench includes forming the first trench in the saw streets extending in the first direction.

33. The method of claim 32, wherein forming the second trench includes forming the second trench in a backside of the wafer beneath the integrated circuits.

34. The method of claim 33, wherein providing the substrate includes providing a bond pad on the first side of the wafer and connecting the bond pad to the conductor in the through via.

35. The method of claim 34, wherein providing the substrate includes dicing the substrate through the through via.