Method and structure for forming relatively dense conductive layers

• US 7,375,411 B2
• Filed: 06/03/2004
• Issued: 05/20/2008
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Zhang, Ligang
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/860,081
• Publication Number:
  US 20050269668A1
• Time in Patent Office: 1,447 Days
• Field of Search: 257/532, 257/508, 257/531, 257/659, 257/700, 257/773
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A region of high metal density may be placed in metal layers proximate to an area of low metal density below an inductor on an integrated circuit without violating manufacturing design rules for reducing manufacturing defects and without substantially impacting performance of the inductor. These results are achieved by including a transitional region that includes conductive structures electrically isolated from each other between the region of high metal density and the region of low metal density. The transitional region has a structure that allows a negligible amount of current flow to be induced in the structure.

Claims

1. An integrated circuit comprising:

a substrate;

a plurality of integrated circuit layers formed above the substrate;

an inductor at least partially formed in another integrated circuit layer above the substrate;

at least one region of low conductor density vertically displaced from the inductor and including at least one portion of each of the plurality of integrated circuit layers;

at least one transitional region including at least one portion of each of the plurality integrated circuit layers, the at least one transitional region disposed adjacent to the at least one region of low conductor density in each of the integrated circuit layers;

at least one region of high conductor density including at least one portion of each of the plurality of integrated circuit layers, the at least one region of high conductor density disposed adjacent to the at least one transitional region, the at least one transitional region disposed between the at least one region of low conductor density and the at least one region of high conductor density; and

a plurality of conductive structures formed in the at least one transitional region, the plurality of conductive structures being electrically isolated from each other;

wherein the inductor is vertically displaced from the plurality of integrated circuit layers including the at least one region of low conductor density, the at least one region of high conductor density, and the at least one transitional region;

wherein the at least one region of high conductor density has a conductor density in the range of 20% to 80%,

wherein the at least one region of low conductor density is substantially void of conductive structures.

2. The integrated circuit, as recited in claim 1, wherein individual one of the plurality of conductive structures includes respective conductive structures in one of the plurality of integrated circuit layers, which are electrically isolated from each other, and are electrically coupled to respective conductive structures in one or more other integrated circuit layers of the plurality of integrated circuit layers, the conductive structures being electrically isolated from each other, to form vertical conductive structures electrically isolated from each other.

3. The integrated circuit, as recited in claim 2, wherein at least one of the vertical conductor structures is coupled to a fixed potential through a high impedance structure.

4. The integrated circuit, as recited in claim 1, wherein at least one of the conductor structures is coupled to a fixed potential through a high impedance structure.

5. The integrated circuit, as recited in claim 1, wherein the at least one transitional region comprises:

at least one transitional region that extends from the inductor in a first direction; and

at least one transitional region that extends from the inductor in a second direction.

6. The integrated circuit, as recited in claim 1, wherein the at least one transitional region extends parallel to a direction of current in the inductor.

7. The integrated circuit, as recited in claim 1, wherein the at least one transitional region is proximate to a projected edge of the inductor.

8. The integrated circuit, as recited in claim 7, wherein the at least one transitional region is between the at least one region of high conductor density and the projected edge of the inductor.

9. The integrated circuit, as recited in claim 7, wherein the at least one transitional region is within a projected perimeter of the inductor.

10. The integrated circuit, as recited in claim 1, wherein the at least one transitional region is at least partially underneath the inductor.

11. The integrated circuit, as recited in claim 1, wherein the at least one transitional region has a conductor density of at least approximately 50%.

12. The integrated circuit, as recited in claim 1, wherein a quality factor associated with the inductor is not substantially degraded by inclusion of the at least one transitional region.

13. The integrated circuit, as recited in claim 1, wherein inductance of the inductor is not substantially degraded by inclusion of the at least one transitional region.

14. The integrated circuit, as recited in claim 1, wherein performance of the inductor is not substantially degraded by inclusion of the at least one transitional region.

18. The integrated circuit, as recited in claim 1, wherein the inductor is formed entirely above the plurality of integrated circuit layers and the at least one region of low conductor density is formed between the inductor and the substrate.

21. The integrated circuit, as recited in claim 1, wherein no substantial current flows in the at least one transitional region.

27. The integrated circuit, as recited in claim 1, wherein the inductor is formed entirely above the at least one region of low conductor density.

28. The integrated circuit, as recited in claim 1, wherein the inductor is formed at least partially above the at least one transitional region.

15. An apparatus comprising:

a substrate;

a plurality of integrated circuit layers formed above the substrate;

an inductor at least partially formed in another integrated circuit layer above the substrate;

at least one region of low conductor density vertically displaced from the inductor and including at least one portion of each of the plurality of integrated circuit layers;

at least one region of high conductor density including at least one portion of each of the plurality of integrated circuit layers; and

at least one means for protecting from manufacturing defects the at least one region of high conductor density, the means for protecting being formed in the plurality of integrated circuit layers and formed proximate to the at least one region of low conductor density, the means for protecting inducing substantially no current in response to an electromagnetic field generated by the inductor,

wherein the inductor is vertically displaced from the plurality of integrated circuit layers including the at least one region of low conductor density, the at least one region of high conductor density, and the at least one means from protecting;

wherein the at least one region of high conductor density includes conductive layers having conductor density in the range of 20% to 80%,

wherein the at least one region of low conductor density is void of conductive structures.

16. The apparatus, as recited in claim 15, wherein the at least one means for protecting is proximate to a projected outer edge of the inductor.

17. The apparatus, as recited in claim 15, further comprising:

means for setting at least one potential of the at least one means for protecting to a known voltage.

23. The apparatus, as recited in claim 15, wherein the inductor, the at least one region of high conductor density, the at least one region of low conductor density, and the at least one means for protecting are formed on a single integrated circuit substrate.

24. The apparatus, as recited in claim 15, wherein the at least one means for protecting includes a plurality of conductive structures electrically isolated from each other.

25. The apparatus, as recited in claim 23, wherein the inductor is formed in at least a first integrated circuit layer above the plurality of integrated circuit layers and the at least one region of low conductor density is formed between the inductor and the integrated circuit substrate.

29. The apparatus, as recited in claim 15, wherein the inductor is formed entirely above the at least one region of low conductor density.

30. The apparatus, as recited in claim 15, wherein the inductor is formed at least partially above the at least one means for protecting.

19. An integrated circuit comprising:

a substrate;

plurality of integrated circuit layers formed above the substrate;

an inductor at least partially formed in another integrated circuit layer above the substrate;

at least one region of low conductor density vertically displaced from the inductor and including at least one portion of each of the plurality of integrated circuit layers;

at least one transitional region including at least one portion of each of the plurality of integrated circuit layers, the at least one transitional region disposed adjacent to the at least one region of low conductor density in each of the integrated circuit layers;

at least one region of high conductor density including at least one portion of each of the plurality of integrated circuit layers, the at least one region of high conductor density disposed immediately adjacent to the at least one transitional region, the at least one transitional region disposed immediately adjacent to the at least one region of low conductor density and disposed between the at least one region of low conductor density and the at least one region of high conductor density; and

a plurality of conductive structures formed in the at least one transitional region, the plurality of conductive structures being electrically isolated from each other;

wherein the inductor is vertically displaced from the plurality of integrated circuit layers including the at least one region of low conductor density, the at least one region of high conductor density, and the at least one transitional region;

wherein the at least one region of high conductor density has a conductor density in the range of 20% to 80%,

wherein the at least one region of low conductor density is substantially void of conductive structures.

20. The integrated circuit, as recited in claim 19, wherein the inductor, the at least one region of high conductor density, and the at least on region of low conductor density are formed on a single integrated circuit substrate.

22. The integrated circuit, as recited in claim 19, wherein no substantial current flows in the at least one transitional region.

26. The integrated circuit, as recited in claim 19, wherein the inductor is formed in at least a first integrated circuit layer above the plurality of integrated circuit layers and the at least one region of low conductor density is formed between the inductor and a substrate of the integrated circuit.

31. The integrated circuit, as recited in claim 19, wherein the inductor is formed entirely above the at least one region of low conductor density.

32. The integrated circuit, as recited in claim 19, wherein the inductor is formed at least partially above the at least one transitional region.