Semiconductor device
First Claim
1. A semiconductor device including a differential level converter circuit that receives a first signal and a phase-inverted signal of the first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal,wherein the differential level converter circuit comprises a first MISFET pair of a first conductivity type for receiving the first signal and the phase-inverted signal;
- of the first signal;
a second MISFET pair of the first conductivity type for improving a withstand voltage of the first MISFET pair;
a third MISFET pair of a second conductivity type having cross-coupled gates for latching the second signal to output; and
a forth MISFET pair of the second conductivity type for ensuring the withstand voltage of the first MISFET pair;
wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair;
wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair;
wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair;
wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair;
wherein a drain of one of the fourth MISFET pair is coupled to a drain of one of the first MISFET pair, and the first signal is inputted to a gate of the one of the fourth MISFET pair; and
wherein a drain of another of the fourth MISFET pair is coupled to a drain of another of the first MISFET pair, and the phase-inverted signal of the first signal is inputted to a gate of the another of the fourth MISFET pair.
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Accused Products
Abstract
A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
28 Citations
15 Claims
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1. A semiconductor device including a differential level converter circuit that receives a first signal and a phase-inverted signal of the first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal,
wherein the differential level converter circuit comprises a first MISFET pair of a first conductivity type for receiving the first signal and the phase-inverted signal; - of the first signal;
a second MISFET pair of the first conductivity type for improving a withstand voltage of the first MISFET pair;
a third MISFET pair of a second conductivity type having cross-coupled gates for latching the second signal to output; and
a forth MISFET pair of the second conductivity type for ensuring the withstand voltage of the first MISFET pair;wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair; wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair; wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair; wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair; wherein a drain of one of the fourth MISFET pair is coupled to a drain of one of the first MISFET pair, and the first signal is inputted to a gate of the one of the fourth MISFET pair; and wherein a drain of another of the fourth MISFET pair is coupled to a drain of another of the first MISFET pair, and the phase-inverted signal of the first signal is inputted to a gate of the another of the fourth MISFET pair. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- of the first signal;
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10. A semiconductor device including a level converter circuit that receives a first signal with an amplitude of a first voltage and outputs a second signal with an amplitude of a second voltage which is larger than the first voltage,
wherein the level converter circuit comprises a first MISFET, a second MISFET and a third MISFET with source-drain paths therein connected in series having the second voltage applying therebetween; - a fourth MISFET, a fifth MISFET and a sixth MISFET with source-drain paths therein connected in series having the second voltage applying therebetween;
a seventh MISFET with a source-drain pathbetween a drain of the first MISFET and the first voltage, and a eighth MISFET with a source-drain path between a drain of the fourth MISFET and the first voltage, wherein the first, second, fourth and fifth MISFETs are a first conductivity type and the third, sixth, seventh and eights MISFETs are a second conductivity type, wherein the first, second and seventh MISFETS receive the first signal at gates therein;
the fourth, fifth and eighth MISFETs receive a phase-inverted signal of the first signal at gates therein,wherein a gate of the third MISFET is coupled to a drain of the sixth MISFET;
a gate of the sixth MISFET is coupled to a drain of the third MISFET,wherein each of the second, third, fifth and sixth MISFETs has a gate insulating film thicker than the gate insulating film of each of the first, fourth, seventh and eighth MISFETs; and
each of the second and fifth MISFETs has a threshold voltage lower than a threshold voltage of each of the first, third, fourth and sixth MISFETS. - View Dependent Claims (11, 12, 13, 14, 15)
- a fourth MISFET, a fifth MISFET and a sixth MISFET with source-drain paths therein connected in series having the second voltage applying therebetween;
Specification