Differential readout from pixels in CMOS sensor
First Claim
Patent Images
1. A method of operating an imaging pixel array of an image sensor, said method comprising:
- sampling a reset and a charge accumulated signal from a desired pixel;
sampling a reset and a comparison signal from a reference pixel, wherein said reference pixel is a desired pixel at a different time; and
using said reset and comparison signals from said reference pixel to offset noise from said desired pixelwherein said reset signal from said desired pixel is sampled simultaneously with said reset signal of said reference pixel.
2 Assignments
0 Petitions
Accused Products
Abstract
The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by using a differential readout of the signal and reset value from the desired pixel compared with the reset value from a reference pixel. In this manner common mode noise can be offset and therefore minimized. In one embodiment of the invention, the reference pixel is the nearest neighbor pixel in the same row. In another embodiment, the reference pixel is the nearest neighboring pixel in a different row.
30 Citations
59 Claims
-
1. A method of operating an imaging pixel array of an image sensor, said method comprising:
-
sampling a reset and a charge accumulated signal from a desired pixel; sampling a reset and a comparison signal from a reference pixel, wherein said reference pixel is a desired pixel at a different time; and using said reset and comparison signals from said reference pixel to offset noise from said desired pixel wherein said reset signal from said desired pixel is sampled simultaneously with said reset signal of said reference pixel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A method of operating an imaging pixel array of an image sensor, said method comprising:
-
sampling a reset and a charge accumulated signal from a desired circuit having a shared floating diffusion node; sampling a reset and a comparison signal from a reference circuit having a shared floating diffusion node, wherein said reference circuit is a desired circuit at a different time; and using said reset and comparison signals from said reference circuit to offset noise from said desired circuit, wherein said reset signal from said desired circuit is sampled simultaneously with said reset signal of said reference circuit. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. An image sensor, comprising:
-
a desired pixel for generating a reset and charge accumulation signal; a reference pixel for generating a reset signal and comparison signal, wherein said reference pixel is a desired pixel at a different time; a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit. - View Dependent Claims (30, 31, 32, 33, 34)
-
-
35. An image sensor, comprising:
-
a desired circuit having a shared floating diffusion node for generating a reset and charge accumulation signal; a reference circuit having a shared floating diffusion node for generating a reset signal and comparison signal, wherein said reference circuit is a desired circuit at a different time; a circuit for sampling and holding said reset and charge accumulated signals generated by said desired circuit and said reset and comparison signals generated by said reference circuit; and a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired circuit and said reset and comparison signals generated by said reference circuit, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired circuit and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired circuit and comparison signal of said reference circuit. - View Dependent Claims (36, 37, 38, 39, 40)
-
-
41. A circuit for sampling and holding signals from a desired and reference pixel, comprising:
-
a first sample and hold circuit to store a first and second signal from a desired pixel, said first circuit adapted to be coupled with a first column line; and a second sample and hold circuit to store a third and fourth signal from a reference pixel, said second circuit adapted to be coupled with a second column line, wherein said reference pixel and said desired pixel are exposed at a substantially same time to a same image, wherein said reference pixel is a desired pixel at a different time. - View Dependent Claims (42, 43, 44, 45, 46)
-
-
47. A circuit for sampling and holding signals from a desired and reference circuit having a shared floating diffusion node, comprising:
-
a first sample and hold circuit to store a first and second signal from a desired circuit having a shared floating diffusion node, said first circuit adapted to be coupled with a first column line; and a second sample and hold circuit to store a third and fourth signal from a reference circuit having a shared floating diffusion node, said second circuit adapted to be coupled with a second column line, wherein said reference circuit is a desired circuit at a different time, where said second sample and hold circuit further comprises; a second sample and hold reset circuit to store a reference circuit reset signal as said third signal from said reference circuit; and a second sample and hold signal circuit to store a reference circuit comparison signal as said fourth signal from said desired circuit, wherein said first and second sample and hold circuits are adapted to simultaneously sample and hold said reset signals of said desired circuit and said reset signal of said reference circuit, and said first and second sample and hold circuits are adapted to simultaneously sample and hold said comparison signal of said reference circuit and said charge accumulated signal of said desired circuit.
-
-
48. A semiconductor chip, comprising:
-
a pixel image sensor, comprising; a desired pixel for generating a reset and charge accumulation signal; a reference pixel for generating a reset signal and comparison signal, wherein said reference pixel is a desired pixel at a different time; a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit. - View Dependent Claims (49, 50, 51, 52, 53)
-
-
54. A processor system, comprising:
-
a central processing unit; pixel image sensor coupled to said central processing unit, comprising; a desired pixel for generating a reset and charge accumulation signal; a reference pixel for generating a reset signal and comparison signal, wherein said reference pixel is a desired pixel at a different time; a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signals of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit. - View Dependent Claims (55, 56, 57, 58, 59)
-
Specification