Method of feedback control of ESC voltage using wafer voltage measurement at the bias supply output

• US 7,375,947 B2
• Filed: 02/07/2007
• Issued: 05/20/2008
• Est. Priority Date: 05/10/2005
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hoffman, Daniel J., Shannon, Steven C., Kim, Kwang-Soo, Burns, Douglas H., Lee, Wonseok, Yang, Jang Gyoo
• Primary Examiner(s): Sherry; Michael
• Assistant Examiner(s): Kitov; Zeev
• Application Number:
  US11/672,362
• Publication Number:
  US 20070127188A1
• Time in Patent Office: 468 Days
• Field of Search: 361/234, 361/233, 279/128, 216/67
• US Class Current: 361/234
• CPC Class Codes: H01J 37/32706 Polarising the substrate
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: Y10T 279/23 with magnetic or electrostatic means

Abstract

In a plasma reactor having an electrostatic chuck, wafer voltage is determined from RF measurements at the bias input using previously determined constants based upon transmission line properties of the bias input, and this wafer voltage is used to accurately control the DC wafer clamping voltage.

Claims

1. In a plasma reactor having an electrostatic chuck (ESC) supporting a wafer to be processed, a method of processing the wafer while controlling an ESC clamping voltage, comprising:

applying RF bias power to said ESC from a bias power source at an input to said ESC and applying a D.C. voltage at said input to said ESC from a D.C. voltage source;

measuring voltage and current near said input to produce a measured voltage and a measured current;

providing a wafer voltage signal as a sum of said measured voltage and said measured current multiplied by first and second coefficients respectively, said wafer voltage signal representing the voltage on a wafer supported on said ESC; and

computing a wafer clamping voltage as a difference between a D.C. component of said wafer voltage signal and said D.C. voltage from said D.C. voltage source, and controlling said D.C. voltage to regulate said wafer clamping voltage.

2. The method of claim 1 wherein the step of controlling said D.C. voltage comprises minimizing a difference between said wafer clamping voltage and a target clamping voltage.

3. The method of claim 2 further comprising selecting said target clamping voltage in accordance with a desired wafer temperature.

4. The method of claim 1 wherein the step of applying RF bias power comprises applying RF bias power through a coaxial transmission line, and wherein said first and second coefficients comprise a voltage coefficient and a current coefficient, respectively, of a transmission line equation corresponding to said coaxial transmission line.

5. The method of claim 4 wherein said wafer support pedestal comprises a conductive grid coupled to the output end of said coaxial transmission line, and:

the step of providing said wafer voltage signal comprises multiplying said sum by a correction factor comprising ratio between a grid-to-wafer impedance, Z_wafer, and a grid-to-ground impedance, Z_grid.

6. The method of claim 5 further comprising:

producing said voltage and current coefficients in accordance with said transmission line equation and storing said coefficients in a memory associated with said reactor;

producing said grid-to-ground impedance, Z_grid, in accordance with a grid-to-ground transformation corresponding to said transmission line and storing said grid-to-ground impedance in said memory; and

producing said grid-to-wafer impedance, Z_wafer, in accordance with a grid-to-wafer transformation of said ESC, and storing said grid-to-wafer impedance in said memory.

7. In a plasma reactor having a wafer voltage controller and an electrostatic chuck (ESC) for clamping a wafer to be processed in the reactor, a method for determining a wafer voltage for use by the controller, comprising:

applying plasma RF bias power comprising first and second frequency components, f(1), f(2), respectively, to an input of said ESC;

providing measurement signals representing first and second frequency components of a measured voltage and first and second frequency components of a measured current at said input of said ESC;

providing first and second frequency components of a wafer voltage signal as, respectively, a first sum of the first frequency components of said measured voltage and measured current multiplied by first and second coefficients respectively, and a second sum of the second frequency components of said measured voltage and measured current multiplied by third and fourth coefficients, respectively; and

computing a D.C. wafer voltage by combining D.C. components of said first and second frequency components of said wafer voltage with a correction factor comprising a product of said D.C. components of said first and second components of said wafer voltage raised to a selected power and multiplied by a selected coefficient.

8. The method of claim 7 wherein said selected power is about 0.5 and said selected coefficient is about 0.3.

9. The method of claim 7 wherein said selected power is about 0.43 and said selected coefficient is about one.

10. The method of claim 7 wherein said reactor comprises a D.C. supply voltage source connected to said ESC, said method further comprising:

controlling the voltage of said D.C. supply voltage source of said ESC to govern a wafer clamping voltage comprising a difference between said D.C. wafer voltage and the voltage of said D.C. supply voltage of said ESC.

11. The method of claim 10 wherein the step of controlling comprises minimizing a difference between said clamping voltage and a target clamping voltage.

12. The method of claim 11 further comprising selecting said target clamping voltage in accordance with a desired wafer temperature.

13. The method reactor of claim 7 wherein:

said first and second coefficients comprise a first frequency voltage coefficient and a first frequency current coefficient, respectively, of a transmission line equation corresponding to a coaxial transmission line connected to said input of said ESC; and

said third and fourth coefficients comprise a second frequency voltage coefficient and a second frequency current coefficient, respectively, of a transmission line equation corresponding to said coaxial transmission line.

14. The method of claim 13 wherein the step of providing said clamping voltage further comprises:

multiplying said first sum by a correction factor comprising a ratio between a first frequency component of a grid-to-wafer impedance, Z_wafer(f1), and a first frequency component of a grid-to-ground impedance, Z_grid(f1);

multiplying said second sum by a correction factor comprising a ratio between a second frequency component of a grid-to-wafer impedance, Z_wafer(f2), and a second frequency component of a grid-to-ground impedance, Z_grid(f2).

15. The method of claim 14 further comprising:

producing said first and second frequency voltage and current coefficients in accordance with a transmission line model and storing said coefficients in a memory associated with said reactor;

producing said first and second frequency component grid-to-ground impedances, Z_grid(f1), Z_grid(f2), in accordance with a grid-to-ground electrical model and storing said impedances in said memory; and

producing said first and second frequency component grid-to-wafer impedances, Z_wafer(f1), Z_wafer(f2) in accordance with a grid-to-wafer electrical model and storing said impedances in said memory.

16. The reactor of claim 7 wherein said first frequency component corresponds to a low frequency on the order of a few MHz, and said second frequency component corresponds to a high frequency on the order of about 10 MHz, and wherein said correction factor compensates for intermodulation between said first and second frequency components.