Data storewidth accelerator
DCFirst Claim
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1. A system comprising:
- a processor comprising a data compression engine for compressing data stored to a data storage device and for decompressing data retrieved from the data storage device;
a programmable logic device, wherein the programmable logic device is programmed by the processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host system;
a non-volatile memory device, for storing logic code associated with the processor, the first interface and the second interface; and
a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller;
wherein the processor further comprises a bandwidth allocation controller for controlling access to the cache memory device by the data compression engine, the first interface and the second interface.
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Abstract
Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration.
367 Citations
25 Claims
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1. A system comprising:
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a processor comprising a data compression engine for compressing data stored to a data storage device and for decompressing data retrieved from the data storage device; a programmable logic device, wherein the programmable logic device is programmed by the processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host system; a non-volatile memory device, for storing logic code associated with the processor, the first interface and the second interface; and a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller;
wherein the processor further comprises a bandwidth allocation controller for controlling access to the cache memory device by the data compression engine, the first interface and the second interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system comprising:
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a processor comprising a data compression engine for compressing data stored to a data storage device; a programmable logic device, wherein the programmable logic device is programmed by the processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host system; a non-volatile memory device, for storing logic code associated with the processor, the first interface and the second interface; and a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller;
wherein the processor further comprises a bandwidth allocation controller for controlling access to the cache memory device by the data compression engine, the first interface and the second interface. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification