Speculative multiaddress atomicity

• US 7,376,800 B1
• Filed: 04/27/2005
• Issued: 05/20/2008
• Est. Priority Date: 09/14/2004
• Status: Active Grant

• Current Assignee: Azul Systems Incorporated
• Original Assignee: Azul Systems Incorporated
• Inventors: Choquette, Jack H., Tene, Gil, Normoyle, Kevin
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US11/117,657
• Time in Patent Office: 1,119 Days
• Field of Search: 711/130, 711/141, 711/144, 711/145, 711/147, 711/148, 711/156
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

Claims

1. A method of performing a plurality of operations in a shared memory system having a plurality of addresses comprising:

entering into a speculative mode;

speculatively performing each of the plurality of operations on addresses in the shared memory system such that the plurality of operations appears atomic to one or more execution threads;

marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state; and

exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

2. A method as recited in claim 1, wherein the shared memory system includes a cache.

3. A method as recited in claim 1, wherein the shared memory system includes a global memory and a plurality of local memories.

4. A method as recited in claim 1, wherein the shared memory system includes a global memory and a plurality of caches.

5. A method as recited in claim 1, wherein the operations are performed atomically.

6. A method as recited in claim 1, wherein the operations are performed on a cache memory.

7. A method as recited in claim 1, further including detecting when a speculatively operated on address is disturbed.

8. A method as recited in claim 7, wherein an address is disturbed when a coherency request is made of that address.

9. A method as recited in claim 7, wherein an address is disturbed when an eviction is received.

10. A method as recited in claim 1, further including aborting the plurality of operations.

11. A method as recited in claim 10, wherein aborting includes setting a reporting mechanism to report an invalid state for addresses in a modified state that have been marked as having been speculatively written.

12. A method as recited in claim 1, further including committing the plurality of operations.

13. A method as recited in claim 1, wherein address states include modify, share, or invalid.

14. A method as recited in claim 1, further including marking the addresses as being in a non-speculative state.

15. A method as recited in claim 1, wherein one or more addresses reside in an L1 cache.

16. A method as recited in claim 1, wherein one or more addresses reside in an L2 cache.

17. A method as recited in claim 1, whereby another cache domain within the shared memory system is not affected.

18. A method as recited in claim 1, wherein an address is a cache line.

19. A method as recited in claim 1, wherein the speculative state is applied to a plurality of caches in the shared memory system.

20. A method as recited in claim 1, wherein the operations include a load or a store operation.

21. A method as recited in claim 1, further including saving original data when a store is performed.

22. A method as recited in claim 1, further including saving original data when the original data is in a non-speculative modified state.

23. A method as recited in claim 1, further including saving original data by storing the original data in a local shadow location.

24. A method as recited in claim 1, further including saving original data by storing the original data to lower level cache before performing a store.

25. A method as recited in claim 1, further including saving original data by storing the original data to memory before performing a store.

26. A method as recited in claim 1, further including retrieving original data from memory.

27. A system for performing a plurality of operations in a shared memory system having a plurality of addresses comprising:

a processor configured to;

enter into a speculative mode;

speculatively perform each of the plurality of operations on addresses in the shared memory system such that the plurality of operations appears atomic to one or more execution threads;

mark addresses in the shared memory system that have been operated on speculatively as being in a speculative state; and

exit the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state; and

a memory coupled with the processor, wherein the memory provides the processor with instructions.

28. A computer program product for performing a plurality of operations in a shared memory system having a plurality of addresses, the computer program product being stored in a computer readable medium and comprising computer instructions for:

entering into a speculative mode;

speculatively performing each of the plurality of operations on addresses in the shared memory system such that the plurality of operations appears atomic to one or more execution threads;

marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state; and

exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.