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Method of timing calibration using slower data rate pattern

  • US 7,376,857 B2
  • Filed: 12/22/2004
  • Issued: 05/20/2008
  • Est. Priority Date: 11/09/2000
  • Status: Expired due to Fees
First Claim
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1. A logic device comprising:

  • means for receiving a calibration bit pattern at said logic device;

    a memory device, said memory device storing said received calibration bit pattern; and

    means for using said stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said logic device to produce a reliable detection of said calibration bit pattern,wherein said receiving means receives said received calibration bit pattern at a first data rate, which is slower than a normal operating data rate at which said logic device usually receives data.

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