Method of timing calibration using slower data rate pattern

• US 7,376,857 B2
• Filed: 12/22/2004
• Issued: 05/20/2008
• Est. Priority Date: 11/09/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Ryan, Kevin J., Lee, Terry R.
• Primary Examiner(s): Trujillo; James K
• Application Number:
  US11/018,384
• Publication Number:
  US 20050204245A1
• Time in Patent Office: 1,245 Days
• Field of Search: 713/401, 713/503
• US Class Current: 713/401
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Claims

1. A logic device comprising:

means for receiving a calibration bit pattern at said logic device;

a memory device, said memory device storing said received calibration bit pattern; and

means for using said stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said logic device to produce a reliable detection of said calibration bit pattern,

wherein said receiving means receives said received calibration bit pattern at a first data rate, which is slower than a normal operating data rate at which said logic device usually receives data.

2. The logic device of claim 1, wherein said reliable detection of said calibration bit pattern is performed at a second data rate approximately equal to said normal operating data rate.

3. The logic device of claim 2, wherein said second data rate is about an integer number of times as fast as said first data rate.

4. The logic device of claim 1, wherein said receiving means comprises means for lowering a frequency of a clock signal used to synchronize said receiving means.

5. The logic device of claim 1, further comprising means for deactivating one of a delay locked loop (DLL) and phase locked loop (PLL) circuits at said logic device at least during receiving of said calibration bit pattern.

6. The logic device of claim 1, wherein said memory device stores only every Nth bit of data received at said first logic device.

7. The logic device of claim 1, further comprising means for receiving a pattern input mode command at said logic device prior to receiving said calibration bit pattern.

8. The logic device of claim 7, wherein said means for receiving said pattern input mode command comprises means for using data paths of said logic device that normally operate at said first data rate.

9. The logic device of claim 7, wherein said means for receiving said pattern input mode command includes means for receiving said command N consecutive times on a command and address bus.

10. The logic device of claim 1, wherein said data path is an address path.

11. The logic device of claim 1, wherein said data path is a command signal path.

12. The logic device of claim 1, wherein said data path is a data bus signal path.

13. The logic device of claim 1, wherein said data path is an input data line signal path.

14. A logic device comprising:

means for receiving a calibration bit pattern at said logic device;

a memory device, said memory device storing said received calibration bit pattern; and

means for using said stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said logic device to produce a reliable detection of said calibration bit pattern,

wherein said memory device stores every bit received at said first logic device, and said using means retrieves only every Nth bit stored by said storing means.

15. The logic device of claim 14, wherein said memory device stores further comprises a linear address counter to count only every Nth address of said received bits.

16. The logic device of claim 14, wherein said using means comprises a test mode circuit to count only every Nth address of said received bits.

17. A logic device comprising:

means for receiving a calibration bit pattern at said logic device;

a memory device, said memory device storing said received calibration bit pattern; and

means for using said stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said logic device to produce a reliable detection of said calibration bit pattern,

wherein said memory device comprises a prefetch demultiplexer that stores only every Nth bit received.

18. A digital logic system comprising:

a first logic device;

a second logic device; and

a calibration circuit on at least one of said first and second devices, said calibration circuit comprising;

means for receiving a calibration bit pattern;

a memory device, said memory device storing said received calibration bit pattern; and

means for using said stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said at least one of said first and second logic devices to produce a reliable detection of said calibration bit pattern,

wherein said receiving means receives said received calibration bit pattern at a first data rate, which is slower than a normal operating data rate at which said logic device usually receives data.