Isolation circuit

• US 7,378,290 B2
• Filed: 08/30/2004
• Issued: 05/27/2008
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Primary Examiner(s): Gurley; Lynne
• Assistant Examiner(s): IM, JUNGHWA M
• Application Number:
  US10/929,898
• Publication Number:
  US 20050026315A1
• Time in Patent Office: 1,366 Days
• Field of Search: 438/18, 438/14, 438/17, 438/53, 438/107, 438/110, 438/11, 438/12, 438/460, 438/462, 324/765, 257/E21.521
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Claims

1. A method of making an isolation circuit, comprising:

forming a first probe pad in one or more scribe lines of a wafer, the first probe pad adapted to receive a control signal from a probe of a test system;

forming a second probe pad in the one or more scribe lines of the wafer and coupled to each of a plurality of microelectronic dice on the wafer, the second probe pad adapted to receive a test signal from another probe of the test system;

forming a third pad coupled to a component formed in a first microelectronic die of the plurality of microelectronic dice on the wafer; and

forming a device in the one or more scribe lines of the wafer, the device coupled to the first probe pad, the second probe pad, and the third pad, the device adapted to selectively transfer the test signal from the second probe pad individually to only the third pad coupled to the component formed in the first microelectronic die in response to the device receiving the control signal from the first probe pad.

2. The method of claim 1, wherein forming the device comprises forming the device as one of a metal oxide semiconductor (MOS) device, a multiplexor, a conductive jumper, and a fuse device.

3. The method of claim 1, wherein forming at least one of the first probe pad and the second probe pad includes forming the first probe pad and the second probe pad in a redistribution layer.

4. The method of claim 1, wherein forming the device includes forming an anti-fuse type device.

5. The method of claim 1, wherein forming a first probe pad in one or more scribe lines of a wafer and forming a second probe pad in the one or more scribe lines of the wafer includes forming the first probe pad in a first scribe line and forming the second probe pad in a second scribe line that is different from the first scribe line.

6. A method of making an isolation circuit, comprising:

forming a first probe pad in one or more scribe lines of a wafer, the first probe pad to receive a test signal from a probe of a test system;

forming a second part pad coupled to a component;

forming a first device in the one or more scribe lines of the wafer, the first device coupled to the first probe pad and the second part pad and adapted to selectively transfer the test signal from the first probe pad to the second part pad in response to the first device receiving a control signal;

forming a control pad in the one or more scribe lines of the wafer, the control pad coupled to the first device, the control pad operable to receive the control signal and to apply the control signal to the first device; and

forming a second device coupled to the control pad and to the first device, the second device adapted to selectively prevent the first device from transferring the test signal from the first probe pad to the second part pad.

7. The method of claim 6, further comprising providing a wireless identification circuit to provide the control signal.

8. The method of claim 6, wherein the first device is an N-channel transistor, and the second device selectively connects the gate of the N-channel transistor to ground potential.

9. The method of claim 6, forming the second device includes forming the second device on a mutant die on the wafer.

10. A method of making a microelectronic die, comprising:

forming a first probe pad in one or more scribe lines, the first probe pad adapted to receive a control signal from a probe of a test system;

forming a second probe pad in the one or more scribe lines, the second probe pad adapted to receive a test signal from another probe of the test system;

forming a third pad coupled to a component formed on the microelectronic die; and

forming a device in the one or more scribe lines, the device coupled to the first probe pad, the second probe pad, and the third pad, the device adapted to selectively transfer the test signal from the second probe pad to the third pad in response to the device receiving the control signal from the first probe pad.

11. The method of claim 10, further comprising:

forming a second device adapted to selectively prevent the second probe pad from being coupled to the third pad during a predetermined use of the microelectronic die.

12. A method of making a microelectronic die, comprising:

forming a first probe pad in one or more scribe lines, the first probe pad to receive a test signal from a probe of a test system;

forming a second pad in the one or more scribe lines, the second pad coupled to a component;

forming a first device coupled to the first probe pad and the second pad, the first device adapted to selectively transfer the test signal from the first probe pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first device from transferring the test signal from the first probe pad to the second pad;

wherein forming the first device and the second device includes forming at least one of the first device and the second device on a sacrifice die.

13. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first probe pad in one or more scribe lines of a wafer, the first probe pad adapted to receive a control signal from a probe of a test system;

forming a second probe pad in the one or more scribe lines of the wafer, the second probe pad adapted to receive a test signal from another probe of the test system;

forming a third pad coupled to one of the processor and the memory system; and

forming a first device in the one or more scribe lines of the wafer, the first device coupled to the first probe pad, the second probe pad, and the third pad, the first device adapted to selectively transfer the test signal from the second robe pad to only the third pad in response to the first device receiving the control signal from the first probe pad.

14. The method of claim 13, further comprising forming a second device adapted to selectively prevent the first device from selectively transferring the test signal from the second probe pad to the third pad during a predetermined use of the electronic system.

15. The method of claim 13, wherein forming the first probe pad in one or more scribe lines of a wafer and forming the second probe pad in the one or more scribe lines of the wafer includes forming the first probe pad in a first scribe line and forming the second probe pad in a second scribe line that is different from the first scribe line.

16. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first probe pad in one or more scribe lines, the first probe pad to receive a test signal from a probe of a test system;

forming a second probe pad in the one or more scribe lines, the second probe pad coupled to one of the processor and the memory system;

forming a first device adapted to selectively transfer the test signal from the first probe pad to the second probe pad in response to a control signal; and

forming a second device to selectively prevent the the first device from selectively transferring the test signal from the first probe pad to the second probe pad;

wherein forming the first device and the second device includes forming at least one of the first device and the second device on a sacrifice die.

17. The method of claim 16, wherein forming the first probe pad in one or more scribe lines of a wafer and forming the second probe pad in the one or more scribe lines of the wafer includes forming the first probe pad in a first scribe line and forming the second probe pad in a second scribe line that is different from the first scribe line.

18. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test probe pad associated with each of the plurality of microelectronic dies, the test probe pad operable to receive the test signal from a probe of a tester system;

operating a device associated with each microelectronic die to transfer the test signal from the test probe pad to a further pad if the microelectronic die is good, wherein the further pad is connected to the microelectronic die; and

preventing the test signal from being applied to the microelectronic die if the die is defective by applying a control signal to the device through a control probe pad, the control probe pad being coupled to the device associated with the defective die, the control probe pad operable to receive the control signal from another probe of the tester system;

wherein the test probe pad, the control probe pad, and the device associated with each microelectronic die are formed in one or more scribe lines on the semiconductor wafer.

19. The method of claim 18, wherein operating the device comprises one of:

sending a gate signal to operate a MOS transistor;

sending a signal to operate a multiplexor;

forming a conductive jumper; and

operating an anti-fuse device.

20. The method of claim 18, wherein preventing the test signal from being applied to the microelectronic die comprises one of:

sending a gate signal to prevent a MOS transistor from operating;

operating a fuse device; and

operating a multiplexor to prevent the test pad from being coupled to the further pad.

21. The method of claim 18, further comprising:

receiving a radio frequency signal to operate the device if the microelectronic die is good.

22. The method of claim 18, wherein the further pad is a part pad.

23. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test probe pad associated with each of the microelectronic dies, the test probe pad operable to receive the test signal from a probe of a tester system;

operating a device associated with each microelectronic die to transfer the test signal from the test probe pad to a further pad associated with each microelectronic die if the microelectronic die is good, wherein the further pad is connected to the microelectronic die;

preventing the test signal from being applied to the microelectronic die if the die is defective by applying a control signal to the device through a control probe pad, the control probe pad being coupled to the device associated with the defective die, the control probe pad operable to receive the control signal from another probe of the tester system; and

preventing the device from transferring the test signal to each associated further pad during a selected use of the microelectronic die;

wherein the test probe pad, the control probe pad, and the device associated with each microelectronic die are formed in one or more scribe lines on the semiconductor wafer.

24. The method of claim 23, wherein the device is an N-channel transistor and wherein preventing each test probe pad from transferring the test signal to each associated further pad comprises grounding a gate of the N-channel transistor.

25. The method of claim 23, wherein the device is a P-channel transistor and wherein preventing each test probe pad from being coupled to each associated further pad comprises applying a high signal to a gate of the P-channel transistor.

26. The method of claim 23, wherein the further pad is a part pad.