Multiple dielectric FinFET structure and method

• US 7,378,357 B2
• Filed: 11/01/2005
• Issued: 05/27/2008
• Est. Priority Date: 03/18/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Clark, William F. Jr.
• Primary Examiner(s): Smoot; Stephen W
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US11/264,446
• Publication Number:
  US 20060054978A1
• Time in Patent Office: 938 Days
• Field of Search: 438/778, 438/761, 438/275, 438/981, 438/300, 257/401, 257/347, 257/E27.112
• US Class Current: 438/778
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

Claims

1. A method of forming a fin-type field effect transistor (FinFET) structure, said method comprising:

patterning fins on a substrate;

forming a first gate dielectric on said fins;

protecting first fins using a mask;

removing said first gate dielectric from unprotected second fins;

removing said mask from said first fins; and

forming an additional gate dielectric on said second fins and on said first gate dielectric that covers said first fins to form different thicknesses of gate dielectrics on said first fins when compared to said second fins.

2. The method in claim 1, further comprising utilizing said fins in different types of transistors on said substrate, wherein one type of transistor includes gate dielectrics having a first thickness and a second type of transistor includes gate dielectrics having a second thickness different than said first thickness.

3. The method in claim 1, further comprising utilizing said fins in multiple-fin transistors.

4. The method in claim 1, wherein said process of forming an additional gate dielectric forms multiple layers of dielectric over said first fins and forms only said additional gate dielectric over said second fins.

5. The method in claim 1, wherein said process of patterning said fins forms a cap over said fins.

6. The method in claim 5, wherein said cap comprises a different material than said gate dielectrics.

7. A method of forming a fin-type field effect transistor (FinFET) structure, said method comprising:

patterning fins on a substrate;

forming a first gate dielectric on said fins;

protecting first fins using a mask;

removing said first gate dielectric from unprotected second fins;

removing said mask from said first fins;

forming an additional gate dielectric on said second fins and on said first gate dielectric that covers said first fins to form different thicknesses of gate dielectrics on said first fins when compared to said second fins and to form different fin thicknesses;

doping ends of said fins to form source and drain regions separated by a central channel regions of said fins; and

forming a gate conductor over said channel regions, wherein said gate dielectrics insulate said channel regions from said gate conductor.

8. The method in claim 7, further comprising utilizing said fins in different types of transistors on said substrate, wherein one type of transistor includes gate dielectrics having a first thickness and a second type of transistor includes gate dielectrics having a second thickness different than said first thickness.

9. The method in claim 7, further comprising utilizing said fins in multiple-fin transistors.

10. The method in claim 7, wherein said process of forming an additional gate dielectric forms multiple layers of dielectric over said first fins and forms said additional gate dielectric only over said second fins.

11. The method in claim 7, wherein said process of patterning said fins forms a cap over said fins.

12. The method in claim 11, wherein said cap comprises a different material than said gate dielectrics.

13. A method of forming a fin-type field effect transistor (FinFET) structure, said method comprising:

patterning fins on a substrate;

forming a first gate dielectric on said fins;

protecting first fins using a mask;

removing said first gate dielectric from unprotected second fins;

removing said mask from said first fins;

forming an additional gate dielectric on said second fins and on said first gate dielectric that covers said first fins to form different thicknesses of gate dielectrics on said first fins when compared to said second fins; and

utilizing said fins in different types of transistors on said substrate, wherein one type of transistor includes gate dielectrics having a first thickness and a second type of transistor includes gate dielectrics having a second thickness different than said first thickness.

14. The method in claim 13, further comprising utilizing said fins in multiple-fin transistors.

15. The method in claim 13, wherein said process of forming an additional gate dielectric forms multiple layers of dielectric over said first fins and forms said additional gate dielectric only over said second fins.

16. The method in claim 13, wherein said process of patterning said fins forms a cap over said fins.

17. The method in claim 16, wherein said cap comprises a different material than said gate dielectrics.