Gate stacks

• US 7,378,712 B2
• Filed: 08/08/2006
• Issued: 05/27/2008
• Est. Priority Date: 10/01/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Tucker, Deborah A., Shank, Steven M., Martin, Dale W., Triplett, Michael C.
• Primary Examiner(s): Pham; Hoai v
• Application Number:
  US11/463,039
• Publication Number:
  US 20070194385A1
• Time in Patent Office: 658 Days
• Field of Search: 257337-338, 257368-369, 257/900, 257/E27.06, 257/E27.062
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

Claims

1. A semiconductor structure, comprising:

(a) a semiconductor region;

(b) a gate stack on top of the semiconductor region, the gate stack including

(i) a gate dielectric region on top of the semiconductor region,

(ii) a first gate polysilicon region on top of the gate dielectric region, and

(iii) a second gate polysilicon region on top of the first gate polysilicon region, the second gate polysilicon region being doped;

(c) a dielectric spacer layer in direct physical contact with the semiconductor region, the gate dielectric region, and the first and second gate polysilicon regions,

wherein a reference direction is defined as being perpendicular to a first common interfacing surface of the first gate polysilicon region and the dielectric spacer layer and being parallel to a second common interfacing surface of the gate dielectric region and the semiconductor region,

wherein a first thickness in the reference direction of the dielectric spacer layer measured through a first point of the dielectric spacer layer is less than a second thickness in the reference direction of the dielectric spacer layer measured through a second point of the dielectric spacer layer,

wherein a first straight line goes through both the first point of the dielectric spacer layer and a third point inside the first gate polysilicon region and is parallel to the reference direction, and

wherein a second straight line goes through both the second point of the dielectric spacer layer and a fourth point inside the second gate polysilicon region and is parallel to the reference direction.

2. The semiconductor structure of claim 1,

wherein the second gate polysilicon region is doped with n-type dopants, and

wherein the first gate polysilicon region is undoped.

3. The semiconductor structure of claim 1, wherein the first gate polysilicon region is undoped.

4. The semiconductor structure of claim 1, wherein a first width in the reference direction of the first gate polysilicon region is greater than a second width in the reference direction of the second gate polysilicon region.

5. The semiconductor structure of claim 1, wherein the dielectric spacer layer comprises silicon dioxide.

6. The semiconductor structure of claim 5, wherein the gate dielectric region comprises silicon dioxide.

7. The semiconductor structure of claim 6,

wherein the second gate polysilicon region is doped with n-type dopants, and

wherein the first gate polysilicon region is undoped.