Integrated stress relief pattern and registration structure

• US 7,378,720 B2
• Filed: 04/03/2007
• Issued: 05/27/2008
• Est. Priority Date: 06/01/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fu, Chung-min, Lin, Huang-Sheng, Chen, Hsien-Wei, Harn, Yu-Chyi
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/695,665
• Publication Number:
  US 20070187845A1
• Time in Patent Office: 420 Days
• Field of Search: 257/620, 257785-776
• US Class Current: 257/620
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Claims

1. A semiconductor die having an integrated circuit region formed in a substrate comprising:

at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate proximate to the integrated circuit region; and

at least one registration feature formed within the at least one DCCF region, wherein the registration feature comprises a first material and a second material different than the first material, and wherein the second material surrounds the first material.

2. The semiconductor die of claim 1, wherein the registration feature comprises a reverse tone composition providing a high contrast for registration identification.

3. The semiconductor die of claim 1, wherein the first material comprises a dielectric material.

4. The semiconductor die of claim 3, wherein the dielectric material comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, a low-k material.

5. The semiconductor die of claim 1, wherein the second material comprises a metal material.

6. The semiconductor die of claim 1, wherein the registration feature comprises a laser fuse mark.

7. The semiconductor die of claim 1, further comprising at least one corner stress relief zone in the at least one die-corner-circuit-forbidden region.

8. The semiconductor die of claim 1, wherein the registration feature includes an alignment mark.

9. The semiconductor die of claim 8, wherein the alignment mark comprises at least one mark selected from the group consisting of a photo alignment mark and a scanning electron microscope mark.

10. The semiconductor die of claim 8, wherein the alignment mark comprises at least one monitor mark.

11. The semiconductor die of claim 10, wherein the at least one monitor mark comprises at least one mark selected from the group consisting of a critical dimension mark, a doping monitor pad, a chemical mechanical planarization monitor pad, and an etching monitor pad.