Semiconductor device chip and semiconductor device chip package

• US 7,378,747 B2
• Filed: 05/09/2006
• Issued: 05/27/2008
• Est. Priority Date: 05/11/2005
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Jong-Kee
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US11/429,973
• Publication Number:
  US 20060255468A1
• Time in Patent Office: 749 Days
• Field of Search: 257/786, 257/778, 257/758, 257/706, 257/707, 257/780, 257/781, 257/207, 257/208, 257/210
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A semiconductor device chip includes channel blocks each of which includes channels, each of the channels including unit devices placed in a substrate and well regions; first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side; normal bumps for transferring the data signals received by the first metal interconnection lines through first external interconnection lines to be connected to the external side; second metal interconnection lines placed between the channel blocks, each of the second metal interconnection lines being connected to one of the substrate and a corresponding well region; and first heat transfer bumps placed over the second metal interconnection lines to receive the heat generated during driving the channel blocks through the second metal interconnection lines and transfer the received heat to second external interconnection lines to be connected to the external side.

Claims

1. A semiconductor device chip, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a plurality of second metal interconnection lines placed between the channel blocks, each of the second metal interconnection lines being connected to one of the substrate and a corresponding well region; and

a plurality of first heat transfer bumps placed over the second metal interconnection lines to receive the heat generated during driving the channel blocks through the second metal interconnection lines and transfer the received heat to a plurality of second external interconnection lines to be connected to the external side.

2. The semiconductor device chip of claim 1, wherein the first heat transfer bumps includes:

a plurality of 1-1 bumps respectively connected to metal interconnection lines connected to the substrate among the second metal interconnection lines; and

a plurality of 1-2 bumps respectively connected to metal interconnection lines connected to the well regions among the second metal interconnection lines.

3. The semiconductor device chip of claim 2, further comprising:

a power supplying unit for receiving one of a power voltage and a ground voltage through a power input terminal from the external side to drive the channel blocks;

a plurality of third metal interconnection lines respectively connected to one of the substrate and the well regions of the channel blocks;

a plurality of heat transfer lines respectively connected to the third metal interconnection lines;

a plurality of first connection lines corresponding to the heat transfer lines, wherein each of the first connection line has one side connected to one side of a corresponding heat transfer line and the other side connected to the power input terminal;

a plurality of second connection lines corresponding to the heat transfer lines, wherein each of the second connection lines is connected to the other side of the corresponding heat transfer line; and

a plurality of second heat transfer bumps respectively connected to the second connection lines to transfer the heat received from the substrate and the well regions through the third metal interconnection lines, the heat transfer lines and the second connection lines.

4. The semiconductor device chip of claim 3, wherein the second heat transfer bumps are placed on edges of the semiconductor device chip.

5. The semiconductor device chip of claim 4, wherein the second heat transfer bumps are placed over a passivation layer region corresponding to where an input/output terminal for inputting and outputting the data signals is formed.

6. The semiconductor device chip of claim 5, wherein the heat transfer lines are arranged separately and independently from each other for each of the channel blocks or the heat transfer lines are electrically connected to each other throughout the channel blocks.

7. The semiconductor device chip of claim 6, wherein the heat transfer lines includes:

a first heat transfer line connected to the substrate through one selected from the third metal interconnections; and

a second heat transfer line electrically separated from the first heat transfer line and connected to a part of the well regions through one selected from the third metal interconnection lines.

8. The semiconductor device chip of claim 7, wherein the second heat transfer bumps includes:

a 2-1 heat transfer bump connected to the first heat transfer line through one selected from the first connection lines; and

a 2-2 heat transfer bump connected to the second heat transfer line through one selected from the second connection lines.

9. The semiconductor device chip of claim 8, wherein the third metal interconnection lines includes:

a 3-1 metal interconnection line connected to the substrate; and

a 3-2 metal interconnection line electrically isolated from the 3-1 metal interconnection line and connected to the well region.

10. The semiconductor device chip of claim 5, further comprising:

a plurality of fourth metal interconnection lines respectively connected to one of the substrate and the well regions arranged in the channel blocks; and

a plurality of third heat transfer bumps connected to the fourth metal interconnection lines to receive the heat generated during driving the channel blocks through the fourth metal interconnection lines and transfer the received heat to a plurality of third external interconnection lines to be connected to the external side.

11. The semiconductor device chip of claim 10, wherein the channel blocks include:

latch units for latching the data signals inputted through input terminals;

a digital/analog (D/A) converter for converting digital signals outputted from the latch units to analog signals; and

an output circuit unit for amplifying and outputting the analog signals.

12. The semiconductor device chip of claim 3, wherein the second metal interconnection lines includes:

a plurality of 2-1 metal interconnection lines for receiving one of the power voltage and the ground voltage transferred from the power supplying unit and providing one of the received power voltage and the received ground voltage to one of the substrate and the well regions; and

a plurality of 2-2 metal interconnection lines of which one sides are connected to one of the substrate and the well regions, and the other sides are connected to the first heat transfer bumps.

13. The semiconductor device chip of claim 12, wherein the number of the 2-1 metal interconnection lines is identical to that of the 2-2 metal interconnection lines are same.

14. A semiconductor device chip, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a power supplying unit for receiving one of a power voltage and a ground voltage through a power input terminal from the external side to drive the channel blocks;

a plurality of second metal interconnection lines respectively connected to one of the substrate and the well regions of the channel blocks;

a plurality of heat transfer lines respectively connected to the second metal interconnection lines;

a plurality of first connection lines corresponding to the heat transfer lines, wherein each of the first connection line has one side connected to one side of a corresponding heat transfer line and the other side connected to the power input terminal;

a plurality of second connection lines corresponding to the heat transfer lines, wherein each of the second connection lines is connected to the other side of the corresponding heat transfer line; and

a plurality of first heat transfer bumps respectively connected to the second connection lines to transfer the heat received from the substrate and the well regions through the second metal interconnection lines, the heat transfer lines and the second connection lines.

15. The semiconductor device chip of claim 14, wherein the second heat transfer bumps are placed on edges of the semiconductor device.

16. The semiconductor device chip of claim 15, wherein the first heat transfer bumps are placed over a passivation layer region corresponding to where an input/output terminal for inputting and outputting the data signals is formed.

17. The semiconductor device chip of claim 16, wherein the heat transfer lines are arranged separately and independently from each other for each of the channel blocks or the heat transfer lines are electrically connected to each other throughout the channel blocks.

18. The semiconductor device chip of claim 17, wherein the second metal interconnection lines includes:

a 2-1 metal interconnection line connected to the substrate; and

a 2-2 metal interconnection line electrically isolated from the 2-1 metal interconnection line and connected to the well region.

19. The semiconductor device chip of claim 18, wherein the heat transfer lines includes:

a first heat transfer line connected to the substrate through the 2-1 metal interconnection line; and

a second heat transfer line electrically separated from the first heat transfer line and connected to the well region through the 2-2 metal interconnection line.

20. The semiconductor device chip of claim 19, wherein the first heat transfer bumps includes:

a 1-1 heat transfer bump connected to a 2-1 connection line connected to the first heat transfer line; and

a 1-2 heat transfer bump connected to a 2-2 connection line connected to the second heat transfer line, wherein the 2-1 heat transfer bump and the 2-2 heat transfer bump are electrically isolated from each other.

21. The semiconductor device chip of claim 20, further comprising:

a plurality of third metal interconnection lines respectively connected to one of the substrate and the well regions of the channel blocks; and

a plurality of third heat transfer bumps connected to the third metal interconnection lines to receive the heat generated during driving the channel blocks through the third metal interconnection lines and transfer the received heat to a plurality of third external interconnection lines to be connected to the external side.

22. The semiconductor device chip of claim 21, wherein the channel blocks include:

latch units for latching the data signals inputted through the input terminals;

a digital/analog (D/A) converter for converting digital signals outputted from the latch units to analog signals; and

an output circuit unit for amplifying and outputting the analog signals.

23. A semiconductor device chip, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a plurality of second metal interconnection lines placed between the channel blocks, each of the second metal interconnection lines being connected to one of the substrate and a corresponding well region; and

a plurality of first heat transfer bumps placed over the channel blocks, connected to the second metal interconnection lines, and transferring the heat received from one of the substrate and the well regions through a plurality of first external interconnection lines to be connected to the external side.

24. The semiconductor device chip of claim 23, wherein the first heat transfer bumps includes:

a plurality of 2-1 bump respectively connected to metal interconnection lines connected to the substrate among the second metal interconnection lines; and

a plurality of 2-2 bumps respectively connected to metal interconnection lines connected to the well regions among the second metal interconnection lines.

25. The semiconductor device chip of claim 24, further comprising:

a power supplying unit for receiving one of a power voltage and a ground voltage through a power input terminal from the external side to drive the channel blocks;

a plurality of third metal interconnection lines respectively connected to one of the substrate and the well regions of the channel blocks;

a plurality of heat transfer lines connected to the third metal interconnection lines;

a plurality of first connection lines corresponding to the heat transfer lines, wherein each of the first connection line is connected to the heat transfer lines corresponding to the power input terminal;

a plurality of second connection lines corresponding to the heat transfer lines, wherein each of the second connection lines is connected to the other side of the corresponding heat transfer line; and

a plurality of second heat transfer bumps respectively connected to the second connection lines to transfer the heat received from the substrate and the well regions through the third metal interconnection lines, the heat transfer lines and the second connection lines.

26. The semiconductor device chip of claim 25, wherein the second heat transfer bumps are placed on edges of the semiconductor device chip.

27. The semiconductor device chip of claim 26, wherein the second heat transfer bumps are placed over an upper portion of a passivation layer region where an input/output terminal for inputting and outputting the data signals is formed.

28. The semiconductor device chip of claim 27, wherein the heat transfer lines are arranged separately and independently from each other for each of the channel blocks or the heat transfer lines are electrically connected to each other throughout the channel blocks.

29. The semiconductor memory device of claim 28, wherein the third metal interconnection lines include:

a 3-1 metal interconnection line connected to the substrate; and

a 3-2 metal interconnection line electrically isolated from the 3-1 metal interconnection line and connected to the well region.

30. The semiconductor device chip of claim 29, wherein the heat transfer lines includes:

a first heat transfer line connected to the substrate through the 3-1 metal interconnection line; and

a second heat transfer line electrically separated from the first heat transfer line and connected to parts of the well regions through the 3-2 metal interconnection line.

31. The semiconductor device chip of claim 30, wherein the second heat transfer bumps includes:

a 2-1 heat transfer bump connected to a 2-1 connection line connected to the first heat transfer line;

a 2-2 heat transfer bump connected to a 2-2 connection line connected to the second heat transfer line, wherein the 2-1 heat transfer bump and the 2-2 heat transfer bump are electrically isolated from each other.

32. The semiconductor device chip of claim 31, wherein the channel blocks include:

latch units for latching the data signals inputted through input terminal;

a digital/analog (D/A) converter for converting digital signals outputted from the latch units to analog signals; and

an output circuit unit for amplifying and outputting the analog signals.

33. The semiconductor device chip of claim 23, wherein the second metal interconnection lines includes:

a plurality of 2-1 metal interconnection lines for receiving one of the power voltage and the ground voltage transferred from the power supplying unit and providing one of the received power voltage and the received ground voltage to one of the substrate and the well region; and

a plurality of 2-2 metal interconnection lines of which one sides are connected to one of the substrate and the well regions, and the other sides are connected to the first heat transfer bumps.

34. The semiconductor device chip of claim 33, wherein the number of the 2-1 metal interconnection lines is identical to that of the 2-2 metal interconnection lines are same.

35. A semiconductor chip device, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a plurality of second metal interconnection lines placed between the channel blocks, each of the second metal interconnection lines being connected to one of the substrate and a corresponding well region;

a plurality of first heat transfer bumps placed over the second metal interconnection lines to receive the heat generated during driving the channel blocks through the second metal interconnection lines and transfer the received heat to a plurality of second external interconnection lines to be connected to the external side; and

a supporting substrate including the first external interconnection lines and the second external interconnection lines connected to the first heat transfer bumps.

36. The semiconductor device chip of claim 35, wherein the first external interconnection lines and the second external interconnection lines are thin copper film interconnection lines.

37. The semiconductor device chip of claim 35, wherein the supporting substrate is one of a film and a glass substrate.

38. The semiconductor device chip of claim 35, wherein the supporting substrate is a substrate used in one selected from the group consisting of a chip on film (COF) technology, a chip on glass (COG) technology and a taper carrier package (TCP) technology.

39. A semiconductor device chip, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a power supplying unit for receiving one of a power voltage and a ground voltage through a power input terminal from the external side to drive the channel blocks;

a plurality of second metal interconnection lines respectively connected to one of the substrate and the well regions of the channel blocks;

a plurality of heat transfer lines respectively connected to the second metal interconnection lines;

a plurality of first connection lines corresponding to the heat transfer lines, wherein each of the first connection line has one side connected to one side of a corresponding heat transfer line and the other side connected to the power input terminal;

a plurality of second connection lines corresponding to the heat transfer lines, wherein each of the second connection lines is connected to the other side of the corresponding heat transfer line;

a plurality of first heat transfer bumps respectively connected to the second connection lines to transfer the heat received from the substrate and the well regions to a plurality of second external interconnection lines through the second metal interconnection lines, the heat transfer lines and the second connection lines; and

a supporting substrate including the first external interconnection lines and the second external interconnection lines respectively connected to the first heat transfer bumps.

40. The semiconductor device chip of claim 39, wherein the first external interconnection lines and the second external interconnection liens are thin copper film interconnection lines.

41. The semiconductor device chip of claim 39, wherein the supporting substrate is one of a film and a glass substrate.

42. The semiconductor device chip of claim 39, wherein the supporting substrate is a substrate used in one selected from the group consisting of a chip on film (COF) technology, a chip on glass (COG) technology and a taper carrier package (TCP) technology.

43. A semiconductor device chip, comprising:

a plurality of channel blocks each of which includes a plurality of channels, each of the channels including a plurality of unit devices placed in a substrate and a plurality of well regions arranged in the substrate;

a plurality of first metal interconnection lines connected to the unit devices comprising the channels to receive and transfer data signals from and to the external side;

a plurality of normal bumps for transferring the data signals received by the first metal interconnection lines through a plurality of first external interconnection lines to be connected to the external side;

a power supplying unit for receiving one of a power voltage and a ground voltage through a power imputer terminal from the external side to drive the channel blocks;

a plurality of second metal interconnection placed between the channel blocks, each of the second metal interconnection lines being connected to one of the substrate and the corresponding well region;

a plurality of heat transfer bumps placed over the channel blocks and respectively connected to the second metal interconnection lines to transfer the heat transferred from the substrate and the well regions through the second metal interconnection lines; and

a supporting substrate including the first external interconnection lines and the second external interconnection line connected to the first heat transfer bumps.

44. The semiconductor device chip of claim 43, wherein the first external interconnection lines and the second external interconnection liens are thin copper film interconnection lines.

45. The semiconductor device chip of claim 43, wherein the supporting substrate is one of a film and a glass substrate.

46. The semiconductor device chip of claim 43, wherein the supporting substrate is a substrate used in one selected from the group consisting of a chip on film (COF) technology, a chip on glass (COG) technology and a taper carrier package (TCP) technology.