Method and apparatus for digital calibration of an analog-to-digital converter

• US 7,378,999 B1
• Filed: 03/06/2007
• Issued: 05/27/2008
• Est. Priority Date: 03/06/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: McGrath, John, Collins, Anthony J.
• Primary Examiner(s): Mai; Lam T
• Application Number:
  US11/714,361
• Time in Patent Office: 448 Days
• Field of Search: 341120-155
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1028 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/14 Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

Method and apparatus for digital calibration of an analog-to-digital converter (ADC). One example relates to calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution. The A/D conversion system includes an ADC that generates an output having N most significant bits (MSBs) and M least significant bits (LSBs) (i.e., an N+M bit resolution). An offset calibration circuit is configured to determine an offset in the ADC and to compensate the N+M bit output using the offset to provide an N+M bit offset corrected output. A gain calibration circuit is configured to determine a gain correction factor for the ADC and to compensate the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

Claims

1. An apparatus for calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution, the apparatus comprising:

an analog-to-digital converter (ADC) configured to generate an output having N most significant bits (MSBs) and M least significant bits (LSBs), where N and M are integers greater than zero;

an offset calibration circuit coupled to the ADC, the offset calibration circuit being configured to determine an offset in the ADC and compensate the output of the ADC using the offset to provide an N+M bit offset corrected output; and

a gain calibration circuit coupled to the offset calibration circuit, the gain calibration circuit being configured to determine a gain correction factor for the ADC, and compensate the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

2. The apparatus of claim 1, further comprising:

control logic configured to;

select a shorted signal input to the ADC and control the offset calibration circuit to determine the offset based on an output code produced by the ADC after converting the shorted signal input; and

select a reference voltage input to the ADC and control the gain calibration circuit to determine the gain correction factor based on an output code produced by the ADC after converting the reference voltage input.

3. The apparatus of claim 2, wherein the gain correction factor includes a signed fractional portion, and wherein the gain calibration circuit includes a multiplier block configured to determine a sum of the N+M bit offset corrected output and a product of the N+M bit offset corrected output and the signed fractional portion.

4. The apparatus of claim 3, wherein the multiplier block includes an unsigned multiplier coupled to an adder.

5. The apparatus of claim 3, wherein the gain calibration circuit comprises:

a subtractor configured to subtract an output of the multiplier block from an ideal code for the reference voltage to generate an error;

a first register configured to store a minimum error;

a comparator configured to compare an absolute value of the error with the minimum error;

a coefficient generator configured to generate values for the signed fractional portion of the gain correction factor; and

a second register configured to store one of the values for the signed fractional portion corresponding with the minimum error.

6. An analog-to-digital (A/D) conversion system having an N-bit resolution, the conversion system comprising:

an analog-to-digital converter (ADC) having an analog input and an output having N most significant bits (MSBs) and M least significant bits (LSBs), where N and M are integers greater than zero;

an offset calibration circuit having an input, a control input, and an output, the input of the offset calibration circuit being coupled to the output of the ADC, the output of the offset calibration circuit having a width of N+M bits;

a gain calibration circuit having an input, a control input, and an output, the input of the gain calibration circuit being coupled to the output of the offset calibration circuit, the output of the gain calibration circuit having a width of N bits; and

control logic coupled to the control input of the offset calibration circuit and the control input of the gain calibration circuit.

7. The conversion system of claim 6, further comprising:

an analog multiplexer having a control input, a first input, a second input, a third input, and an output, the first input configured to receive an input analog voltage, the second input being shorted, the third input configured to receive a reference voltage, and the output being coupled to the analog input of the ADC; and

wherein the control logic is coupled to the control input of the analog multiplexer.

8. The conversion system of claim 7, wherein the control logic is configured to:

drive the analog multiplexer to select the second input and control the offset calibration circuit to determine the offset based on an output code produced by the ADC after converting the second input; and

drive the analog multiplexer to select the third input and control the gain calibration circuit to determine the gain correction factor based on an output code produced by the ADC after converting the third input.

9. The conversion system of claim 6, wherein the gain calibration circuit comprises:

a multiplexer having a first input, a second input, a control input, and an output, the control input of the multiplexer being coupled to the control logic;

a multiplier block having a first input, a second input, and an output, the first input of the multiplier block being coupled to the output of the multiplexer, the second input of the multiplier block being coupled to the output of the offset calibration circuit; and

binary search logic having a first input, a second input, a first output, and a second output, the first input of the binary search logic being coupled to the output of the multiplier block, the second input of the binary search logic being configured to receive an ideal code for a reference voltage, the first output of the binary search logic being coupled to the first input of the multiplexer, and the second output of the binary search logic being coupled to the second output of the multiplexer.

10. The conversion system of claim 9, wherein the binary search logic comprises:

a subtractor having inputs respectively coupled to the first and second inputs of the binary search logic and an output;

a first register having a data input, an enable input, and an output, the data input of the first register coupled to the output of the subtractor;

a comparator having a first input, a second input, and an output, the first input of the comparator being coupled to the output of the subtractor, the second input of the comparator being coupled to the output of the first register, the output of the comparator being coupled to the enable input of the first register;

a coefficient generator having an input and an output, the input of the coefficient generator configured to receive a most significant bit (MSB) of the output of the subtractor, the output of the coefficient generator being coupled to the first output of the binary search logic; and

a second register having a data input, an enable input, and an output, the data input of the second register being coupled to the output of the coefficient generator, the enable input of the second register being coupled to the output of the comparator, and the output of the second register being coupled to the second output of the binary search logic.

11. The conversion system of claim 9, further comprising:

overflow/underflow and saturation logic coupled to the output of the multiplier block and configured to receive a most significant bit (MSB) of the output of the offset calibration circuit.

12. The conversion system of claim 9, further comprising:

an absolute value circuit coupled between the output of the ADC and the second input of the multiplier.

13. The conversion system of claim 12, wherein the absolute value circuit is configured to invert bits of the output of the ADC without adding one if the output of the ADC is negative.

14. The conversion system of claim 9, wherein the gain correction factor includes a signed fractional portion, and wherein the multiplier block is configured to determine a sum of the output of the offset calibration circuit and a product of the output of the offset calibration circuit and the signed fractional portion.

15. The conversion system of claim 14, wherein the multiplier block includes an unsigned multiplier coupled to an adder.

16. A method of calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution, the method comprising:

generating, at an analog-to-digital converter (ADC), an output having N most significant bits (MSBs) and M least significant bits (LSBs), where N and M are integers greater than zero;

determining an offset in the ADC;

compensating an output of the ADC using the offset to provide an N+M bit offset corrected output;

determining a gain correction factor for the ADC; and

compensating the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

17. The method of claim 16, wherein determining the offset in the ADC comprises:

selecting a shorted signal input to the ADC;

comparing an output code produced by the ADC after converting the shorted signal input to an ideal output code for the shorted signal input; and

determining the offset based on results of the comparison.

18. The method of claim 17, wherein compensating the output of the ADC comprises:

summing the offset and the output of the ADC.

19. The method of claim 16, wherein the gain correction factor includes a signed fractional portion, and wherein compensating the N+M bit offset corrected output comprises:

computing product of the N+M bit offset corrected output and the signed fractional portion; and

summing the product with the N+M bit offset corrected output.

20. The method of claim 19, wherein determining the gain correction factor comprises:

(a) selecting a reference voltage input to the ADC;

(b) assigning initial values to a coefficient, the fractional portion, and a minimum error;

(c) compensating the N+M bit offset corrected output using the coefficient to generate a calibrated output;

(d) computing an error between the calibrated output and an ideal code for the reference voltage;

(e) if an absolute value of the error is less than the minimum error, assigning the absolute value of the error to the minimum error and assigning the coefficient to the fractional portion;

(f) adjusting the coefficient; and

(g) repeating steps (c) through (f) a plurality of times.