Scalable high performance 3D graphics

• US 7,379,067 B2
• Filed: 12/15/2005
• Issued: 05/27/2008
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Gamehancement LLC (Jeffrey M. Gross)
• Original Assignee: Michael F. Deering
• Inventors: Deering, Michael F., Lavelle, Michael G.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Hsu, Joni
• Application Number:
  US11/305,474
• Publication Number:
  US 20060092162A1
• Time in Patent Office: 894 Days
• Field of Search: 345501-506, 345/522, 345/520, 345/519, 345/530, 345/536, 345/544, 345/545, 345/552, 345/581, 345/582, 709/251
• US Class Current: 345/506
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 5/70 Denoising; Smoothing

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Claims

1. A method of rendering graphics using a rendering computation comprising a rasterization pipeline stage, a sample fill pipeline stage and a convolution stage, said stages performed by a plurality of nodes interconnected in a ring topology, individual nodes containing a rasterization pipeline stage and/or both a sample fill pipeline stage and a convolution stage, the method comprising:

assigning interleaves of a super-sampled buffer to respective local memories of the plurality of interconnected nodes, creating a distributed super-sampled frame buffer, said interleaves dedicated to sample fill pipeline stages and/or convolution stages in said nodes;

receiving a sequence of graphic driver commands;

determining graphic commands in accordance with the sequence of graphic driver commands;

assigning the graphic commands to ones of the plurality of interconnected nodes that contain rasterization pipeline stages, this assignment being independent of the assignment of interleaves;

sending, via the ring topology, graphics primitive loop packets specifying the graphic commands to the assigned interconnected nodes;

performing, by at least one of the interconnected nodes, a rasterization pipeline stage of the rendering computation in accordance with the graphics command assigned to the respective nodes to generate corresponding draw pixel loop packets, wherein ones of the interconnected nodes have texture information stored in the local memory, the texture information dedicated to the rasterization pipeline stage in that node;

sending, via the ring topology, by at least one of the nodes performing rasterization, draw pixel loop packets specifying a command for a sample fill pipeline stage of the rendering computation to ones of the plurality of interconnected nodes that contain sample fill pipeline stages in a manner dependent on the assignments of interleaves;

performing, by the ones of the interconnected nodes that receive a sample fill command, a sample fill pipeline stage of the rendering computation, in accordance with the respective received sample fill commands, a result being update of information in the super-sampled buffer interleaves assigned to the respective nodes;

sending, via the ring topology, video pixel loop packets specifying a convolution to ones of the plurality of interconnected nodes that contain convolution stages in a manner dependent on the assignments of interleaves;

performing, by one or more of the interconnected nodes, a convolution stage of the rendering computation, in accordance with information in the interleaves of the super-sampled frame buffer; and

wherein at least one of the interconnected nodes is configured to perform both the rasterization pipeline stage and the sample fill pipeline stage.

2. The method of claim 1, wherein receiving a sequence of graphic driver commands is performed by an Interface Chip in the plurality of interconnected nodes.

3. The method of claim 1, wherein determining graphic commands in accordance with the sequence of graphic driver commands is performed by an Interface Chip in the plurality of interconnected nodes.

4. The method of claim 1, wherein assigning the graphic commands is performed by an Interface Chip in the plurality of interconnected nodes.

5. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation is performed by at least one Graphics Chip in the plurality of interconnected nodes.

6. The method of claim 1, wherein the sample fill pipeline stage of the rendering computation is performed by at least one Graphics Chip in the plurality of interconnected nodes.

7. The method of claim 1, wherein the convolution stage of the rendering computation is performed by at least one Graphics Chip in the plurality of interconnected nodes.

8. The method of claim 1, wherein at least one Graphics Chip in the plurality of interconnected nodes is configured to perform the rasterization pipeline stage, the sample fill pipeline stage, and the convolution stage.

9. The method of claim 1, wherein assigning the graphic commands uses a load balancing method.

10. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes a clip checking operation.

11. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes a clipping operation if needed.

12. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes vertex shading.

13. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes scan converting.

14. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation performs programmable shading.

15. The method of claim 14, wherein the rasterization pipeline stage of the rendering computation includes performing programmable shading on vertices.

16. The method of claim 14, wherein the rasterization pipeline stage of the rendering computation includes performing programmable shading on pixels.

17. The method of claim 14, wherein the rasterization pipeline stage of the rendering computation includes performing programmable shading on micropolygon vertices.

18. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation process includes texture operations.

19. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes displacement mapping.

20. The method of claim 1, wherein each of the interconnected nodes can perform a substantial portion of the graphics rendering pipeline.

21. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation process includes tessellation of higher order surfaces.

22. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation process includes multicasting “

projected to screen space boundaries”

of the results of tessellating and shading graphics primitives to targeted ones of the interconnected nodes, along with the plane equation of Z.

23. The method of claim 1, wherein performing the convolution stage includes initiating information gathering and processing from the interconnected nodes by an Interface Chip.

24. The method of claim 1, wherein the texture information includes a texture map.

25. The method of claim 1, wherein all of the interconnected nodes have a copy of the texture information.

26. The method of claim 1, wherein more than one of the interconnected nodes have the same texture information.

27. The method of claim 1, further including, sending a rendered image to the interconnected nodes for use as a texture.

28. The method of claim 1, further including, after the convolution stage, sending a rendered image to the interconnected nodes for use as a texture.

29. The method of claim 1, wherein the interconnected nodes are connected in a double ring schematic.

30. The method of claim 1, wherein the interconnected nodes are connected using at least one shortcut connection.

31. The method of claim 1, wherein the rasterization pipeline stage of the rendering computation includes accessing texture maps, wherein this accessing includes applications of texture filtering techniques to the texture map data prior to the texture accessing returning information.

32. The method of claim 31, wherein said texture filtering techniques include one or more of direct access, nearest neighbor access, bi-linear filtering, tri-linear filtering, bi-linear MIP mapping, tri-linear MIP mapping, anisotropic filtering, summed area filtering, procedural textures, bump mapping, displacement mapping, percentage closer shadow filtering, and deep shadow map filtering.

33. The method of claim 1, wherein the rasterization pipeline stage of the rendering pipeline includes surface tessellation.

34. The method of claim 33, wherein the surface tessellation includes the tessellation of surface primitives.

35. The method of claim 34, wherein the surface primitives include one or more of polygons, higher order surface primitives, and implicit surfaces.

36. The method of claim 35, wherein the higher order surface primitives includes one or more of conic surfaces, ruled surfaces, surfaces of revolution, Bé

zier patches, B-Spline patches, NURBS patches, sub-division surfaces, and sub-division surfaces with edge and vertex sharpness control.

37. The method of claim 33, wherein the tessellation includes the application of displacement maps.

38. The method of claim 1, wherein the sample fill pipeline stage includes a conditional sample update function.

39. The method of claim 1, wherein at least one of the interconnected nodes performs the sample fill pipeline stage locally within the node without any additional communications outside the node.

40. The method of claim 1, wherein the rendering computation includes generation of one or more of rendered images, textures, texture maps, final rendered images, and shadow maps.

41. The method of claim 1, wherein the convolution stage involves subjecting information gathered from each node to antialiasing processing.

42. The method of claim 41, wherein the antialiasing processing is incrementally performed on each node.

43. The method of claim 1, wherein at least one of the interconnected nodes performs some fraction of the convolution locally within the node without any additional communications outside the node.

44. The method of claim 1, wherein the plurality of interconnected nodes use a single physical connection for all direct information transfer between any two nodes.

45. The method of claim 1, wherein the plurality of interconnected nodes are all connected in a manner that is point to point, unidirectional and of a short physical distance.

46. The method of claim 1, further comprising communication outside the nodes including connection to one or more host computer systems for the transmission of graphics driver commands to the nodes.

47. The method of claim 1, further comprising communication outside of the nodes including connection to one or more host computer systems for the transmission of rendered images from the nodes to the at least one host computer system.

48. The method of claim 1, further comprising communication outside of the nodes including connection to one or more physical images display devices for the transmission of final rendered images from the nodes to the physical images display devices.

49. The method of claim 1, further comprising communication between the plurality of interconnected nodes and a second plurality of interconnected nodes.

50. The method of claim 1, wherein at least one node is formed of a single processing chip and at least one memory chip.

51. The method of claim 1, wherein the rasterization stage of the rendering computation is performed locally by a node without communication to other nodes.

52. A 3D graphics hardware accelerator comprising a plurality of nodes connected to a ring;

each node comprising a loop interface for receiving packets from a neighboring node on the ring and for transmitting packets to another neighboring node on the ring;

each node further comprising a render stage and/or both a sample fill stage and a video output stage;

each of the render stage, sample fill stage and/or video output stage communicating to the ring via the loop interface;

nodes that include a render stage, a sample fill stage and/or a video output stage further comprising a local memory sub-system accessible by the stage(s) via a shared memory access, the local memory sub-system storing a texture store dedicated to the render stage and/or storing an interleave of a super-sampled frame buffer dedicated to the sample fill stage and the video output stage, the interleaves for all nodes collectively creating a distributed super-sampled frame buffer;

each render stage receiving graphics primitive loop packets, executing the graphics rendering specified in the graphics primitive loop packets including accessing the texture store in the local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets;

each sample fill stage receiving draw pixel loop packets and, as specified by the draw pixel loop packets, performing a conditional sample update function of samples and/or pixels in the interleave stored in the local memory sub-system;

each video output stage receiving video pixel loop packets;

as specified by the video pixel loop packets, retrieving samples and/or pixels in the interleave stored in the local memory sub-system and using the retrieved samples and/or pixels to modify the video pixel loop packets; and

transmitting the modified video pixel loop packets;

the nodes collectively containing a sufficient number of render stages, sample fill stages and video output stages connected to the ring to implement a 3D graphics rendering pipeline with those three stages.

53. The 3D graphics hardware accelerator of claim 52 wherein any node that includes at least one of a render stage, a sample fill stage, and a video output stage includes all three of a render stage, a sample fill stage, and a video output stage.

54. The 3D graphics hardware accelerator of claim 52 wherein at least one node connected to the ring comprises an interface unit, the interface unit including a host interface for connecting to a host computer, the interface unit receiving graphics driver commands from the host computer and converting the graphics driver commands to loop packets for transmission over the ring to other nodes.

55. The 3D graphics hardware accelerator of claim 54 wherein all of the nodes connected to the ring are one of two types:

an interface type that includes an interface unit; and

a draw type that includes all three of a render stage, a sample fill stage, and a video output stage.

56. The 3D graphics hardware accelerator of claim 54, wherein the interface unit converts the graphics driver commands to graphic commands, assigns the graphics commands to render stages and transmits the graphics commands to the assigned render stages via the ring.

57. The 3D graphics hardware accelerator of claim 56, wherein the interface unit assigns the graphic commands uses a load balancing method.

58. The 3D graphics hardware accelerator of claim 54, wherein the interface unit further receives modified video pixel loop packets and transmits rendered images based thereon to the host computer.

59. The 3D graphics hardware accelerator of claim 54, wherein the interface unit further transmits rendered images to one or more physical images display devices not on the ring.

60. The 3D graphics hardware accelerator of claim 52, wherein the video output stages further perform convolution.

61. The 3D graphics hardware accelerator of claim 60, wherein the video output stages further perform anti-aliasing.

62. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes a clip checking operation.

63. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes a clipping operation if needed.

64. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes vertex shading.

65. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes scan converting.

66. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes programmable shading on vertices.

67. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes programmable shading on pixels.

68. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes programmable shading on micropolygon vertices.

69. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes computation process includes texture operations.

70. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes displacement mapping.

71. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes programmable shading.

72. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes multicasting “

projected to screen space boundaries”

of the results of tessellating and shading graphics primitives to targeted ones of the interconnected nodes, along with the plane equation of Z.

73. The 3D graphics hardware accelerator of claim 52, wherein all texture stores have copies of the same texture information.

74. The 3D graphics hardware accelerator of claim 52, wherein at least one of the nodes receives a rendered image for storage to the texture store of the local memory sub-system.

75. The 3D graphics hardware accelerator of claim 52, wherein nodes are connected in a double ring.

76. The 3D graphics hardware accelerator of claim 52, wherein at least two of the nodes are connected using at least one shortcut connection.

77. The 3D graphics hardware accelerator of claim 52, wherein the render stage applies a texture filtering technique to a texture map stored in the local memory sub-system.

78. The 3D graphics hardware accelerator of claim 77, wherein said texture filtering techniques include one or more of direct access, nearest neighbor access, bi-linear filtering, tri-linear filtering, bi-linear MIP mapping, tri-linear MIP mapping, anisotropic filtering, summed area filtering, procedural textures, bump mapping, displacement mapping, percentage closer shadow filtering, and deep shadow map filtering.

79. The 3D graphics hardware accelerator of claim 52, wherein the render stage includes surface tessellation.

80. The 3D graphics hardware accelerator of claim 79, wherein the surface tessellation includes the tessellation of surface primitives.

81. The 3D graphics hardware accelerator of claim 80, wherein the surface primitives include one or more of polygons, higher order surface primitives, and implicit surfaces.

82. The 3D graphics hardware accelerator of claim 81, wherein the higher order surface primitives includes one or more of conic surfaces, ruled surfaces, surfaces of revolution, Bé

zier patches, B-Spline patches, NURBS patches, sub-division surfaces, and sub-division surfaces with edge and vertex sharpness control.

83. The 3D graphics hardware accelerator of claim 79, wherein the tessellation includes the application of displacement maps.

84. The 3D graphics hardware accelerator of claim 52, wherein the nodes use a single physical connection for all information transfer on the ring.

85. The 3D graphics hardware accelerator of claim 52, wherein the nodes use point to point, unidirectional links for all information transfer on the ring.

86. The 3D graphics hardware accelerator of claim 52, wherein at least one node is formed of a single processing chip and at least one memory chip.