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Methods and apparatus of stacking DRAMs

  • US 7,379,316 B2
  • Filed: 09/01/2006
  • Issued: 05/27/2008
  • Est. Priority Date: 09/02/2005
  • Status: Active Grant
First Claim
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1. A memory device for electrical connection to a memory bus, the memory device comprising:

  • a plurality of dynamic random access memory (“

    DRAM”

    ) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and

    an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;

    wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.

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