Methods and apparatus of stacking DRAMs
First Claim
Patent Images
1. A memory device for electrical connection to a memory bus, the memory device comprising:
- a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and
an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.
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Abstract
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
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Citations
23 Claims
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1. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; andan interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprisina a memory core of a plurality of cells and accessible at a first speed; andan interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise; a working pool of “
p”
DRAM integrated circuits; anda spare pool of “
q”
DRAM integrated circuits;wherein “
p” and
“
q”
comprise integer values. - View Dependent Claims (7, 8, 9)
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10. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; andan interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise; a working pool of “
p”
DRAM integrated circuits; anda mirrored pool of “
q”
DRAM integrated circuits;wherein “
p” and
“
q”
comprise integer values. - View Dependent Claims (11, 12, 13, 14)
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15. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a memory scheme wherein the plurality of DRAM integrated circuits comprise; “
p”
DRAM integrated circuits used as a working memory device for storing data across the “
p”
DRAM integrated circuits; andat least one additional DRAM integrated circuit for storing additional information for the data stored in the “
p”
DRAM integrated circuits;wherein “
p”
comprises an integer value. - View Dependent Claims (16, 17)
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18. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a socket, coupled to the stacked plurality of DRAM integrated circuits, for adding at least one additional DRAM integrated circuit to the stacked plurality of DRAM integrated circuits. - View Dependent Claims (19)
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20. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; andan interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits includes; at least one DRAM integrated circuit which was incorporated into the memory device at manufacturing time; and at least one DRAM integrated circuit which was incorporated into the memory device at a later time.
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21. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; a printed circuit board; and a socket for mounting the plurality of DRAM integrated circuits in a rank to the printed circuit board.
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22. A memory device for use with a memory bus, the memory bus comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, stacked in a vertical direction, each comprising a memory core of a plurality of cells accessible at low speed; andan interface integrated circuit for providing an interface, at a high speed relative to the low speed, between the DRAM integrated circuits and the memory bus; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.
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23. A memory device for use with a memory bus, the memory bus comprising:
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means for stacking, in a vertical direction, a plurality of dynamic random access memory (“
DRAM”
) integrated circuits each comprising a memory core of a plurality of cells accessible at a first speed; andmeans for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the means for providing the interface is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the means for providing the interface is electrically coupled.
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Specification