Semiconductor device

• US 7,379,328 B2
• Filed: 06/20/2007
• Issued: 05/27/2008
• Est. Priority Date: 03/12/2004
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Osada, Kenichi, Itoh, Kiyoo
• Primary Examiner(s): PHAM, LY D
• Application Number:
  US11/812,641
• Publication Number:
  US 20070263433A1
• Time in Patent Office: 342 Days
• Field of Search: 365/63, 365/210, 365/230.03, 365/163
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

Claims

1. A semiconductor device, comprising:

a plurality of word lines;

a plurality of bit lines intersecting with the plurality of word lines;

a plurality of memory cells disposed on the intersecting points of the plurality of word lines and the plurality of bit lines;

a plurality of dummy bit lines intersecting with the plurality of word lines;

a plurality of dummy memory cells disposed on the intersecting points of the plurality of word lines and the plurality of dummy bit lines;

a plurality of circuits that select columns;

a plurality of circuits that select word lines;

a sense amplifier circuit;

a plurality of write amplifier circuits; and

a memory array including the plurality of memory cells and the plurality of dummy memory cells, the memory array is separated into at least two sub-arrays, each of the memory arrays having two columns of the dummy memory cells,

wherein a high resistance value is written in one of the two columns of the dummy memory cells, and a low resistance value is written in the other one of the two columns of the dummy memory cells.

2. The semiconductor device according to claim 1, wherein, in one of the sub-arrays which is not accessed during reading-out, the data of the two columns of dummy memory cells are read out respectively by the dummy bit lines, and the dummy bit lines are electrically connected upon reading-out.