RFID tag with bist circuits
First Claim
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1. An apparatus, comprising:
- a semiconductor chip for an RFID tag, said semiconductor chip having a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said one or more inputs as a consequence of said one or more inputs having received a wireless signal, said semiconductor chip also having a non-volatile memory, said non-volatile memory to store said RFID tag'"'"'s identification, said semiconductor chip including built-in-self-test (BIST) logic circuitry to test said non-volatile memory while said semiconductor chip is being tested on wafer.
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Abstract
Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer'"'"'s scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag'"'"'s non-volatile memory.
72 Citations
18 Claims
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1. An apparatus, comprising:
a semiconductor chip for an RFID tag, said semiconductor chip having a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said one or more inputs as a consequence of said one or more inputs having received a wireless signal, said semiconductor chip also having a non-volatile memory, said non-volatile memory to store said RFID tag'"'"'s identification, said semiconductor chip including built-in-self-test (BIST) logic circuitry to test said non-volatile memory while said semiconductor chip is being tested on wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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applying a supply voltage to a semiconductor chip for an RFID tag, said semiconductor chip not yet diced from its wafer, said semiconductor chip comprising non-volatile memory and built-in-self-test (BIST) logic circuitry, said supply voltage applied to said semiconductor chip at a die edge of said semiconductor chip for purposes of testing said non volatile memory on wafer, said testing comprising; said BIST logic circuitry generating a write data pattern; and
,writing said write data pattern into said non-volatile memory. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification