Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

• US 7,381,608 B2
• Filed: 12/07/2004
• Issued: 06/03/2008
• Est. Priority Date: 12/07/2004
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman, Pae, Sangwoo, Maiz, Jose A.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/006,218
• Publication Number:
  US 20060121678A1
• Time in Patent Office: 1,274 Days
• Field of Search: 438/216, 438/591, 438/792, 438/926, 257/E21.202
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.

Claims

1. A method for making a semiconductor device comprising:

forming a silicon dioxide layer on a substrate;

adding nitrogen to the silicon dioxide layer to form a nitrided silicon dioxide layer;

forming a sacrificial layer on the nitrided silicon dioxide layer;

forming a pair of spacers on opposite sides of the nitrided silicon dioxide layer;

removing the sacrificial layer to generate a trench between the pair of spacers;

forming a high-k gate dielectric layer on the nitrided silicon dioxide layer and within the trench; and

forming a metal gate electrode on the high-k gate dielectric layer.

2. The method of claim 1 wherein the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

3. The method of claim 1 wherein a rapid thermal nitridation process is applied to form the nitrided silicon dioxide layer, the rapid thermal nitridation process comprising exposing the silicon dioxide layer to ammonia at a temperature of at least about 980°

C.

4. The method of claim 1 wherein:

the nitrided silicon dioxide layer is less than about 10 angstroms thick;

the sacrificial layer is between about 500 angstroms and about 1,100 angstroms thick and comprises polysilicon;

the sacrificial layer is removed by exposing it to an aqueous solution that comprises a source of hydroxide; and

the high-k gate dielectric layer is between about 5 angstroms and about 20 angstroms thick.

5. The method of claim 1 wherein the metal gate electrode comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, an aluminide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

6. A method for making a semiconductor device comprising:

forming a silicon dioxide layer on a substrate;

adding nitrogen to the silicon dioxide layer to form a nitrided silicon dioxide layer;

forming a polysilicon containing layer on the nitrided silicon dioxide layer;

forming a hard mask layer on the polysilicon containing layer;

etching the hard mask layer, the polysilicon containing layer and the nitrided silicon dioxide layer to form a hard mask that covers a patterned polysilicon containing layer and a patterned nitrided silicon dioxide layer;

forming first and second spacers on opposite sides of the patterned polysilicon containing layer and the patterned nitrided silicon dioxide layer;

exposing the patterned polysilicon containing layer to an aqueous solution that comprises a source of hydroxide to remove the patterned polysilicon containing layer, while retaining the patterned nitrided silicon dioxide layer, and to generate a trench that is positioned between the first and second spacers;

forming a high-k gate dielectric layer on the patterned nitrided silicon dioxide layer and within the trench; and

forming a metal gate electrode on the high-k gate dielectric layer.

7. The method of claim 6 wherein:

the nitrided silicon dioxide layer is less than about 10 angstroms thick;

the polysilicon containing layer is between about 500 angstroms and about 1,100 angstroms thick; and

the high-k gate dielectric layer is between about 5 angstroms and about 20 angstroms thick.

8. The method of claim 6 wherein:

the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; and

the metal gate electrode comprises a metal layer that comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, an aluminide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

9. The method of claim 8 wherein the metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, and an aluminide, and has a workfunction that is between about 3.9 eV and about 4.2 eV.

10. The method of claim 8 wherein the metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, and has a workfunction that is between about 4.9 eV and about 5.2 eV.

11. A method for making a semiconductor device comprising:

forming a silicon dioxide layer on a substrate;

adding nitrogen to the silicon dioxide layer to form a nitrided silicon dioxide layer;

forming a polysilicon containing layer on the nitrided silicon dioxide layer;

forming a silicon nitride containing layer on the polysilicon containing layer;

etching the silicon nitride containing layer, the polysilicon containing layer and the nitrided silicon dioxide layer to form first and second silicon nitride containing hard masks that cover first and second patterned polysilicon containing layers and first and second patterned nitrided silicon dioxide layers;

forming first and second spacers on opposite sides of the first patterned polysilicon containing layer and the first patterned nitrided silicon dioxide layer, and forming third and fourth spacers on opposite sides of the second patterned polysilicon containing layer and the second patterned nitrided silicon dioxide layer;

removing the first and second silicon nitride containing hard masks from the first and second patterned polysilicon containing layers;

exposing the first and second patterned polysilicon containing layers to an aqueous solution that comprises a source of hydroxide to remove the first and second patterned polysilicon containing layers, while retaining the first and second patterned nitrided silicon dioxide layers, and to generate a first trench that is positioned between the first and second spacers and a second trench that is positioned between the third and fourth spacers;

forming a high-k gate dielectric layer on the first and second nitrided silicon dioxide layers and within the first and second trenches;

forming a metal layer on the high-k gate dielectric layer;

forming a masking layer on the metal layer, a first part of the masking layer covering a first part of the high-k gate dielectric layer and a second part of the masking layer covering a second part of the high-k gate dielectric layer;

removing the second part of the masking layer while retaining the first part of the masking layer, exposing part of the metal layer;

removing the exposed part of the metal layer to generate a first metal layer that covers the first part of the high-k gate dielectric layer but does not cover the second part of the high-k gate dielectric layer;

removing the first part of the masking layer; and

forming a second metal layer on the first metal layer and on the second part of the high-k gate dielectric layer, the second metal layer covering the first metal layer and covering the second part of the high-k gate dielectric layer.

12. The method of claim 11 wherein the high-k gate dielectric layer is between about 5 angstroms and about 20 angstroms thick and comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

13. The method of claim 11 wherein:

the first metal layer comprises a metal that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, and has a workfunction that is between about 4.9 eV and about 5.2 eV; and

the second metal gate electrode comprises a metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, and an aluminide, and has a workfunction that is between about 3.9 eV and about 4.2 eV.

14. The method of claim 11 wherein the first metal layer comprises a p-type metal layer that is between about 50 angstroms and about 100 angstroms thick, and the second metal layer comprises an n-type metal layer that is between about 50 angstroms and about 100 angstroms thick, and further comprising forming a fill metal on the n-type metal layer.

15. The method of claim 14 wherein the fill metal is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

16. The method of claim 11 wherein a rapid thermal nitridation process is applied to form the nitrided silicon dioxide layer, the rapid thermal nitridation process comprising exposing the silicon dioxide layer to ammonia at a temperature of at least about 980°

C.

17. The method of claim 11 wherein the silicon nitride containing layer is between about 800 angstroms and about 1,000 angstroms thick, and the masking layer comprises a spin-on-glass.

18. The method of claim 11 wherein the first and second patterned polysilicon containing layers are removed by exposing the first and second patterned polysilicon containing layers to an aqueous solution that comprises between about 0.1 percent and about 10 percent by volume of a source of hydroxide that is selected from the group consisting of ammonium hydroxide and tetraethyl ammonium hydroxide.

19. The method of claim 18 wherein the first and second patterned polysilicon containing layers are exposed to the aqueous solution at a temperature that is between about 20°

C. and about 30°

C., the aqueous solution comprising between about 0.1 percent and about 5 percent ammonium hydroxide by volume in deionized water, and wherein sonic energy is applied while the first and second patterned polysilicon containing layers are exposed to the aqueous solution at a frequency of between about 700 KHz and about 1,000 KHz, while dissipating at between about 3 and about 8 watts/cm².

20. The method of claim 18 wherein the first and second patterned polysilicon containing layers are exposed to the aqueous solution for at least about 10 minutes at a temperature that is between about 20°

C. and about 30°

C., the aqueous solution comprising between about 2 percent and about 10 percent tetraethyl ammonium hydroxide by volume in deionized water.