Self-calibrating anti-blooming circuit for CMOS image sensor having a spillover protection performance in response to a spillover condition

• US 7,381,936 B2
• Filed: 10/29/2004
• Issued: 06/03/2008
• Est. Priority Date: 10/29/2004
• Status: Expired due to Fees

• Current Assignee: RE Secured Networks LLC
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Tan, Mehmet Ali, Luo, Jiafu
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US10/975,474
• Publication Number:
  US 20060092300A1
• Time in Patent Office: 1,313 Days
• Field of Search: 250/208.1, 250/214.R, 250/214.1, 257290-292, 257/440, 257249-257, 348308-312
• US Class Current: 250/208.1
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/622 by controlling anti-blooming drains

Abstract

A method and apparatus to provide blooming protection for a pixel in an array while extending dynamic range.

Claims

1. An image sensor array comprising:

a plurality of imager cells, each including a reset transistor and a well;

each imager cell being operable to selectively provide an output signal indicative of the amount of electrons stored in its well;

a master pixel circuit having an output and having operational characteristics similar to those of one or more of the imager cells;

a reference circuit having an output approximately representative of a maximum output of said imager cells;

an amplifier having as a first input the output of said master pixel circuit, having as a second input the output of said reference circuit, and having an output coupled to an input of said master pixel circuit; and

wherein the amplifier output is used to generate a voltage selectively applied to the reset transistors of at least some of said imager cells.

2. The image sensor of claim 1, wherein said voltage selectively applied to the reset transistors of at least some of said imager cells may be adjusted to accommodate different integration times of said imager cells.

3. The image sensor of claim 2, further comprising a digital to analog converter, wherein the output of said digital to analog converter is combined with the output of said amplifier to adjust said voltage selectively applied to the reset transistors of at least some of said imager cells.

4. The image sensor of claim 3, further comprising a memory for storing a plurality of adjusting values corresponding to different exposure times of said imager cells.

5. The image sensor of claim 1, wherein said master pixel circuit output is representative of said output voltage of any one or more of said imager cell when biased in the subthreshold region at a fixed current.

6. The image sensor of claim 1, wherein said amplifier is a differential operational amplifier.

7. A method for preventing blooming in an image sensor array comprising the steps of:

providing a plurality of imager cells, each including a reset transistor and a well;

each imager cell being operable to selectively provide an output signal indicative of the amount of electrons stored in its well;

providing a master pixel circuit having an output and having operational characteristics similar to those of one or more of the imager cells;

providing a reference circuit having an output approximately representative of a maximum output of said imager cells;

providing an amplifier having as a first input the output of said master pixel circuit, having as a second input the output of said reference circuit, and having an output coupled to an input of said master pixel circuit; and

applying a voltage selectively to the reset transistors of at least some of said imager cells by using the amplifier output.

8. The method of claim 7, further comprising the step of:

adjusting said voltage selectively applied to the reset transistors of at least some of said imager cells to accommodate different integration times of said imager cells.

9. The method of claim 8, further comprising the step of:

providing a memory for storing a plurality of adjusting coefficients corresponding to different exposure times of said imager cells.

10. A method for preventing a spillover condition in a photosensitive imager containing a plurality of image cells comprising the steps of:

producing, during an integration time, charge carriers at said imager cells in response to excitation radiation reaching respective imager cells;

during said integration time, storing said charge carriers produced at said imager cell up to approximately a certain number and substantially removing from said imager cell any additional charge carriers produced in excess of that approximate number; and

wherein the removal is accomplished by shunting said additional charge carriers through a reset transistor coupled to said imager cell, said reset transistor being selectively biased with a reset bias voltage determined in part by an output of a servo loop circuit that compares an output of a master pixel circuit having operating characteristics similar to said imager cells and a reference voltage approximately representative of the maximum linear output of said imager cells.

11. The method of claim 10, further comprising the steps of:

providing an adjustment voltage; and

combining the adjustment voltage with said output of the servo loop circuit to determine said reset bias voltage.

12. A photosensitive apparatus, comprising:

a photodetector and a reset transistor located in an imager cell;

a spillover protection device, controlled by an anti-blooming circuit, for applying a bias to said reset transistor in response to a spillover condition.

13. The apparatus of claim 12, wherein said anti-blooming circuit comprises a master pixel circuit, having characteristics substantially identical to operating characteristics of said imager cell, and a reference circuit, having as an output a potential indicative of said spillover condition.

14. The apparatus of claim 13, wherein said reset transistor has a gate, a source, and a drain;

wherein applying a bias to said reset transistor comprises coupling an output of said spillover protection device to the gate; and

wherein said bias is determined by said anti-blooming circuit by comparing an output of the master pixel circuit to an output of a reference circuit that approximates a maximum voltage at which operation said imager cell operates linearly.

15. The apparatus of claim 12, wherein said anti-blooming circuit has an output which is self-calibrating.