Silicon carbide power devices with self-aligned source and well regions
First Claim
1. A silicon carbide power semiconductor device, comprising:
- a first silicon carbide layer having a first conductivity type;
a source region in the first silicon carbide layer and having the first conductivity type, the source region having a higher carrier concentration than a carrier concentration of the first silicon carbide layer and extending to a first surface of the first silicon carbide layer;
a buried region of silicon carbide of the second conductivity type in the first silicon carbide layer adjacent a bottom portion of the source region and at a depth in the first silicon carbide layer greater than a depth of the source region;
a well region of silicon carbide of the second conductivity type in the first silicon carbide layer on a first side of the source region and extending toward the first surface of the first silicon carbide layer, the well region having a lower carrier concentration than a carrier concentration of the buried region;
a plug region of silicon carbide of the second conductivity type on a second side of the source region, opposite the first side of the source region, and extending to the first face of the first silicon carbide layer;
a gate oxide on the first silicon carbide layer, the well region and the source region;
a gate contact on the gate oxide;
a source contact on the plug region and the source region; and
a drain contact on the first silicon carbide layer opposite the first surface of the first silicon carbide layer.
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Abstract
Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.
147 Citations
21 Claims
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1. A silicon carbide power semiconductor device, comprising:
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a first silicon carbide layer having a first conductivity type; a source region in the first silicon carbide layer and having the first conductivity type, the source region having a higher carrier concentration than a carrier concentration of the first silicon carbide layer and extending to a first surface of the first silicon carbide layer; a buried region of silicon carbide of the second conductivity type in the first silicon carbide layer adjacent a bottom portion of the source region and at a depth in the first silicon carbide layer greater than a depth of the source region; a well region of silicon carbide of the second conductivity type in the first silicon carbide layer on a first side of the source region and extending toward the first surface of the first silicon carbide layer, the well region having a lower carrier concentration than a carrier concentration of the buried region; a plug region of silicon carbide of the second conductivity type on a second side of the source region, opposite the first side of the source region, and extending to the first face of the first silicon carbide layer; a gate oxide on the first silicon carbide layer, the well region and the source region; a gate contact on the gate oxide; a source contact on the plug region and the source region; and a drain contact on the first silicon carbide layer opposite the first surface of the first silicon carbide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 20)
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11. A silicon carbide power semiconductor device comprising:
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a first silicon carbide layer having a first conductivity type; a source region in the first silicon carbide layer and having the first conductivity type, the source region having a higher carrier concentration than a carrier concentration of the first silicon carbide layer and extending to a first surface of the first silicon carbide layer, the source region having dopants of the first conductivity type and dopants of a second conductivity type opposite the first conductivity type; a buried region of silicon carbide of the second conductivity type in the first silicon carbide layer adjacent a bottom portion of the source region and at a depth in the first silicon carbide layer greater than a depth of the source region; a well region of silicon carbide of the second conductivity type in the first silicon carbide layer on a first side of the source region and extending toward the first surface of the first silicon carbide layer; a plug region of silicon carbide of the second conductivity type on a second side of the source region, opposite the first side of the source region, and extending to the first face of the first silicon carbide layer; a gate oxide on the first silicon carbide layer, the well region and the source region; a gate contact on the gate oxide; a source contact on the plug region and the source region; and a drain contact on the first silicon carbide layer opposite the first surface of the first silicon carbide layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 21)
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Specification