Trench gate FETs with reduced gate to drain charge
First Claim
Patent Images
1. A field effect transistor comprising:
- a trench extending into a semiconductor region;
a gate dielectric lining the trench sidewalls;
a gate electrode in the trench; and
a channel region in the semiconductor region extending along a sidewall of the trench,wherein the gate dielectric has a non-uniform thickness, a variation in thickness of the gate dielectric along at least a lower portion of the channel region being inversely dependent on a variation in doping concentration in the lower portion of the channel region such that the variation in thickness of the gate dielectric does not increase a threshold voltage of the field effect transistor.
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Abstract
A field effect transistor includes a trench extending into a semiconductor region. The trench has a gate dielectric lining the trench sidewalls and a gate electrode therein. A channel region in the semiconductor region extends along a sidewall of the trench. The gate dielectric has a non-uniform thickness such that a variation in thickness of the gate dielectric along at least a lower portion of the channel region is inversely dependent on a variation in doping concentration in the at least a lower portion of the channel region.
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Citations
23 Claims
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1. A field effect transistor comprising:
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a trench extending into a semiconductor region; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; and a channel region in the semiconductor region extending along a sidewall of the trench, wherein the gate dielectric has a non-uniform thickness, a variation in thickness of the gate dielectric along at least a lower portion of the channel region being inversely dependent on a variation in doping concentration in the lower portion of the channel region such that the variation in thickness of the gate dielectric does not increase a threshold voltage of the field effect transistor. - View Dependent Claims (2, 3, 4, 5)
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6. A field effect transistor comprising:
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a trench extending into a semiconductor region of a first conductivity type; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; a well region of the second conductivity type in the semiconductor region; a source region of the first conductivity type in the well region; and a channel region extending along a trench sidewall in the well region, the channel region being defined by a spacing between the source region and a bottom surface of the well region, the channel region having a doping concentration which decreases from a maximum concentration in the direction from the source region toward a bottom surface of the well region, and the gate dielectric having a uniform thickness along an upper portion of the channel region and a non-uniform thickness along a remaining lower portion of the channel region, the non-uniform thickness of the gate dielectric increasing from a point below the maximum concentration in the direction from the source region to a point below the bottom surface of the well region, wherein a rate at which the non-uniform thickness of the gate dielectric increases is dependent on a rate at which the doping concentration in the corresponding portion of the channel region decreases such that the increase in the gate dielectric thickness does not increase a threshold voltage of the FET. - View Dependent Claims (7, 8)
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9. A field effect transistor comprising:
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a semiconductor region of a first conductivity type; a well region of a second conductivity type in the semiconductor region; a source region of the first conductivity type in the well region; a trench extending into the semiconductor region; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; a channel region extending along a trench sidewall in the well region, the channel region having a channel length defined by a spacing between the source region and a bottom surface of the well region, wherein the gate dielectric has an upper portion with a uniform thickness and a lower portion with a non-uniform thickness, the lower portion of the gate dielectric extending along at least one-half the channel length, wherein a thickness of the gate dielectric at any point along the lower portion of the gate dielectric is greater than the uniform thickness of the gate dielectric, and wherein a thickness of the gate dielectric linearly increases from a point along an upper half of the channel region to a second thickness at a point below the bottom surface of the well region. - View Dependent Claims (10, 11, 12)
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13. A field effect transistor comprising:
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a semiconductor region; a trench extending into the semiconductor region; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; and a channel region extending along a sidewall of the trench, wherein the gate dielectric has an upper portion with a uniform thickness, and a thickness of the gate dielectric linearly increases from a first thickness at a point along an upper half of the channel region to a second thickness at a point near a bottom surface of the gate electrode. - View Dependent Claims (14)
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15. A field effect transistor comprising:
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a semiconductor region of a first conductivity type; a well region of a second conductivity type in the semiconductor region; a source region of the first conductivity type in the well region; a trench extending into the semiconductor region; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; a channel region extending along a trench sidewall in the well region, the channel region having a channel length defined by a spacing between the source region and a bottom surface of the well region, wherein the gate dielectric has an upper portion with a uniform thickness and a lower portion with a non-uniform thickness, the lower portion of the gate dielectric extending along at least one-half the channel length, wherein a thickness of the gate dielectric at any point along the lower portion of the gate dielectric is greater than the uniform thickness of the gate dielectric, and wherein the channel region has a doping concentration which decreases from a maximum value near the source region to a lower value near a bottom surface of the well region, and wherein a variation in thickness of the lower portion of the gate dielectric is inversely dependent on the variation in the doping concentration in the channel region. - View Dependent Claims (16, 17, 18, 20, 21, 22, 23)
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19. A field effect transistor comprising:
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a trench extending into a semiconductor region; a gate dielectric lining the trench sidewalls; a gate electrode in the trench; and a channel region in the semiconductor region extending along a sidewall of the trench, wherein at least a portion of the gate dielectric has a non-uniform thickness which linearly increases along at least a lower portion of the channel region starting from a point along an upper half of the channel region, the linear increase in thickness of the gate dielectric along the at least a lower portion of the channel region being inversely dependent on a variation in doping concentration in the at least a lower portion of the channel region.
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Specification