High density interconnect system having rapid fabrication cycle

• US 7,382,142 B2
• Filed: 05/18/2005
• Issued: 06/03/2008
• Est. Priority Date: 05/23/2000
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Chong, Fu Chiung, Kao, Andrew, McKay, Douglas, Litza, Anna, Modlin, Douglas, Mok, Sammy, Swiatowiec, Frank John, Shan, Zhaohui, Parekh, Nitin
• Primary Examiner(s): Nguyen, Ha Tran
• Assistant Examiner(s): Nguyen, Tung X.
• Application Number:
  US11/133,021
• Publication Number:
  US 20050275418A1
• Time in Patent Office: 1,112 Days
• Field of Search: 324/754, 324/761, 324/762, 324/765, 324/760, 324/158.1, 439/66
• US Class Current: 324/750.25
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49222 forming array of contacts or terminals

Abstract

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

Claims

1. A probe card interface assembly for establishing connections to one or more bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising:

a motherboard having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

a reference plane defined by at least three points located between the lower planar mounting surface of the motherboard and the semiconductor wafer;

a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe chip assembly mounting surface opposite the upper mounting surface;

a mechanism for adjusting the planarity of the reference plane with respect to the semiconductor wafer; and

at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface attached to the probe chip assembly mounting surface of the probe chip assembly mounting system, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein planarity of any of the probing surface and the mounting surface of the probe chip is adjustable through the planarity mechanism.

2. The probe card interface assembly of claim 1, wherein the probe tips are planarized by confining the probe tips in a fixture that is parallel to any of the probing surface and the mounting surface of the probe chip substrate, and applying heat to the probe chip assembly, such that the probe tips conform to the fixture.

3. The probe card interface assembly of claim 1, wherein the planarity adjustment mechanism comprises any of adjustable screws, differential screws, shims, spacers, washers, spring washers, solder bonds, adhesive bonds, springs, and any combination thereof.

4. The probe card interface assembly of claim 1, wherein mounting of the probe chip assembly inherently provides parallelism between any of the probing surface and the mounting surface of the probe chip, and the probe assembly mounting surface of the probe chip assembly.

5. The probe card interface assembly of claim 1, wherein the probe chip assembly is demountable.

6. The probe card interface assembly of claim 1, further comprising:

means for any of measuring and adjusting parallelism between the lower planar mounting surface and any of the probing surface and the mounting surface of the probe chip.

20. The probe card interface assembly of claim 1, wherein the spring probes comprise any of stress metal springs, flexible springs, compliant springs, and elongate resilient probe elements.

7. A probe card interface assembly for establishing connections to one or more bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising:

a motherboard having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

a reference plane defined by at least three points located between the lower planar mounting surface of the motherboard and the semiconductor wafer;

a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe chip assembly mounting surface opposite the upper mounting surface; and

a mechanism for adjusting the planarity of the reference plane with respect to the semiconductor wafer; and

an alternate probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each, of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein the mounting surface of the alternate probe chip assembly is mountable to the lower planar surface of the probe card interface assembly.

8. The probe card interface assembly of claim 7, whereinthe alternate probe chip assembly is mountable in place of the first probe chip assembly to provide planarity without further calibration.

9. A probe card interface assembly for establishing connections to one or more bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising:

a motherboard having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

a reference plane defined by at least three points located between the lower planar mounting surface of the motherboard and the semiconductor wafer;

a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe chip assembly mounting surface opposite the upper mounting surface;

a mechanism for adjusting the planarity of the reference plane with respect to the semiconductor wafer; and

a lower Z-block comprising a substrate having an interposer contacting surface and a probe chip mounting surface opposite the interposer contacting surface, a first plurality of electrical contact pads arranged on the interposer contacting surface, a corresponding second plurality of bonding pads on the probe chip mounting surface, and electrical connections extending from each of the contact pads in the first plurality of bonding pads to each of the corresponding bonding pads in the second plurality of bonding pads; and

an upper interface located between the lower Z-block and the motherboard, comprising a plurality of electrical contacts;

wherein the lower Z-block is attached to the motherboard with the interposer contacting surface oriented to be parallel with the wafer prober mounting surface.

10. The probe card interface assembly of claim 9, wherein the substrate of the lower Z-block comprises any of a ceramic, a multilayered ceramic, and a co-fired ceramic.

11. The probe card interface assembly of claim 9, further comprising:

at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface soldered to the probe chip mounting surface of the lower Z-block, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein the planarity mechanism is controllable to adjust the reference plane to affect planarity between the probing surface and the semiconductor wafer.

wherein planarity of any of the probing surface and the mounting surface of the probe are adjustable through the plananty mechanism.

12. The probe card interface assembly of claim 11, wherein the upper interface comprises any of:

at least one interposer located between the lower Z-block and the mother board, each of the at least one interposer comprising an upper surface and a lower surface opposite the upper surface, a plurality of compliant electrical contacts on the upper surface, a plurality of electrical contacts on the lower surface, and a plurality of electrically conductive connections between the plurality of compliant electrical contacts and the plurality of electrical contacts; and

a motherboard Z-Block having a first surface and a second surface opposite the first surface, and a plurality of solder bonds between the second surface and the motherboard.

13. The probe card interface assembly of claim 12, wherein the motherboard Z-block contains fan-out electrical connections extending there through.

14. The probe card interface assembly of claim 12, wherein the compliant electrical contacts are plated.

15. The probe card interface assembly of claim 12, wherein the plurality of electrical contacts on the lower surface of the interposer comprise any of solder balls and spring probes.

16. The probe card interface assembly of claim 15, wherein the spring probes are plated.

17. The probe card interface assembly of claim 12, further comprising:

means for adjusting parallelism between the probing surface of the probe chip and any of the interposer contacting surface of the lower, Z-block and the upper surface of the interposer.

18. The probe card interface assembly of claim 12, further comprising:

means for any of adjusting parallelism between the lower planar mounting surface and the first surface of the motherboard z-block.

19. The probe card interface assembly of claim 9, wherein the electrical contact pads arranged on the interposer contacting surface of the lower Z-block are spaced at a larger pitch than the spacing of the corresponding second plurality of bonding pads on the probe chip mounting surface of the lower Z-block.

21. A process for establishing connections to bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising the steps of:

providing a motherboard comprising a substrate having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

defining a reference plane by at least three points located between the lower surface of the motherboard and the semiconductor wafer;

providing a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe assembly mounting surface opposite the upper mounting surface; and

adjusting the planarity of the reference plane with respect to the semiconductor wafer; and

providing a probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface attached to the probe chip assembly mounting surface of the probe chip assembly mounting system, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts; and

adjusting the reference plane to affect planarity between any of the probing surface, the mounting surface, and the probe tips of the probe chip and the semiconductor wafer.

22. The process of claim 21, further comprising the steps of:

mounting the mother board to a prober; and

testing at least one integrated device located on a semiconductor wafer;

wherein the probe tips are sufficiently planar to the semiconductor wafer without further adjustment of planarity.

23. The process of claim 21, further comprising the steps of:

confining the probe tips in a fixture that is parallel to any of the probing surface and the bonding surface of the probe chip substrate, and

applying heat to the probe chip assembly, such that the probe tips conform to the fixture.

24. The process of claim 23, further comprising the step of:

plating the probe tips at any of before and after the heating step.

25. The process of claim 21, further comprising the steps of:

removing the probe chip from the probe assembly mounting surface; and

mounting any of the same probe chip and an alternate probe chip to the probe assembly mounting surface to provide planarity without further calibration.

26. The process of claim 21, further comprising any of:

measuring and adjusting parallelism between the reference plane and the lower planar mounting surface.

27. A process for establishing connections to bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising the steps of:

providing a motherboard comprising a substrate having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

defining a reference plane by at least three points located between the lower surface of the motherboard and the semiconductor wafer;

providing a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe assembly mounting surface opposite the upper mounting surface; and

adusting the planarity of the reference plane with respect to the semiconductor wafer; and

providing a lower Z-block comprising a substrate having an interposer contacting surface and a probe chip mounting surface opposite the interposer contacting surface, a first plurality of electrical contact pads arranged on the interposer contacting surface, a corresponding second plurality of bonding pads on the probe chip mounting surface, and electrical connections extending from each of the contact pads in the first plurality of bonding pads to each of the corresponding bonding pads in the second plurality of bonding pads;

providing an upper interface located between the lower Z-block and the mother board, comprising a plurality of electrical contacts; and

attaching the lower Z-block to the mother board with the interposer contacting surface oriented to be parallel with the lower planar mounting surface.

28. The process of claim 27, further comprising the steps of:

.

providing at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface soldered to the probe chip mounting surface of the lower Z-block, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts; and

adjusting the reference plane to affect planarity between the probing surface and the semiconductor wafer.

29. The process of claim 27, wherein the upper interface comprises any of:

at least one interposer located between the lower Z-block and the mother board, each of the at least one interposer comprising an upper surface and a lower surface opposite the upper surface, a plurality of compliant electrical contacts on the upper surface, a plurality of electrical contacts on the lower surface, and a plurality of electrically conductive connections between the plurality of compliant electrical contacts and the plurality of electrical contacts; and

a motherboard Z-Block having a first surface and a second surface opposite the first surface, and a plurality of solder bonds between the second surface and the motherboard.