Method and apparatus for universal program controlled bus architecture

• US 7,382,156 B2
• Filed: 09/01/2005
• Issued: 06/03/2008
• Est. Priority Date: 09/04/1996
• Status: Expired due to Fees

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Pani, Peter M., Ting, Benjamin S.
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/219,597
• Publication Number:
  US 20060202716A1
• Time in Patent Office: 1,006 Days
• Field of Search: 326/39, 326/41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Claims

1. An integrated circuit, comprising:

a programmable logic array comprising;

a plurality of logic cells, wherein the logic cells are organized in two dimensions; and

a first one or more routing resources selectively coupled to the plurality of logic cells;

a second one or more routing resources located adjacent to the programmable logic array the second one or more routing resources being different than the first one or more routing resources;

a plurality of megacells configured to receive inputs and transmit outputs;

wherein each of the plurality of megacells is selectively coupled to the second one or more routing resources; and

wherein the second one or more routing resources are selectively coupled to the programmable logic array.

2. The integrated circuit as set forth in claim 1, wherein each of the plurality of megacells is selectively coupled to the programmable logic array.

3. The integrated circuit as set forth in claim 2, wherein the second one or more routing resources are selectively coupled to at least one of the programmable logic array and each of the plurality of megacells through logic controlled three-stable outputs.

4. The integrated circuit as set forth in claim 3, wherein each of the plurality of megacells comprises a memory block.

5. The integrated circuit as set forth in claim 4, wherein two or more of the plurality of megacells are cascaded to form a single memory block being deeper than one of the plurality of megacells.

6. The integrated circuit as set forth in claim 4, wherein two or more of the plurality of megacells are cascaded to form a single memory block being wider than one of the plurality of megacells.

7. The integrated circuit as set forth in claim 4, wherein four or more of the plurality of megacells are cascaded to form a single memory block being deeper and wider than one of the plurality of megacells.

8. The integrated circuit as set forth in claim 3, wherein each of the plurality of megacells is a dual port SRAM block.

9. The integrated circuit as set forth in claim 8, wherein two or more of the plurality of megacells are cascaded to form a single dual port SRAM block being deeper than one of the plurality of megacells.

10. The integrated circuit as set forth in claim 8, wherein two or more of the plurality of megacells are cascaded to form a single dual port SRAM block being wider than one of the plurality of megacells.

11. The integrated circuit as set forth in claim 8, wherein four or more of the plurality of megacells are cascaded to form a single dual port SRAM block being deeper and wider than one of the plurality of megacells.

12. The integrated circuit as set forth in claim 11, wherein the routing resources comprise interconnection lines.

13. The integrated circuit as set forth in claim 11, wherein each of the first and second groups of routing resources are programmable through switches.

14. A method of operating an integrated circuit having a programmable logic array, comprising:

selectively coupling a first one or more routing resources to a plurality of logic cells of the programmable logic array, wherein the logic cells are organized in two dimensions, wherein a second one or more routing resources is located adjacent to the programmable logic array, the second one or more routing resources being different than the first one or more routing resources;

receiving inputs to and transmitting outputs from a plurality of megacells;

selectively coupling each of the plurality of megacells to the second one or more routing resources; and

selectively coupling the second one or more routing resources to the programmable logic array.

15. The method of claim 14, further comprising selectively coupling the plurality of megacells to the programmable logic array.

16. The method of claim 15, further comprising selectively coupling the second one or more routing resources to at least one of the programmable logic array and the megacells through logic controlled three-stable outputs.

17. The method of claim 16, wherein each of the plurality of megacells comprises a memory block.

18. The method of claim 17, further comprising cascading two or more of the plurality of megacells to form a single memory block being deeper than one of the plurality of megacells.

19. The method of claim 18, wherein cascading comprises selectively coupling data buses of the second one or more routing resources.

20. The method of claim 17, further comprising cascading two or more of the plurality of megacells to form a single memory block being wider than one of the plurality of megacells.

21. The method of claim 20, wherein cascading comprises selectively coupling address buses of the second one or more routing resources.

22. The method of claim 17, further comprising cascading four or more of the plurality of megacells to form a single memory block being deeper and wider than one of the plurality of megacells.

23. The method of claim 22, wherein cascading comprises selectively coupling data buses and address buses of the second one or more routing resources.

24. The method of claim 17, further comprising cascading two or more of the plurality of megacells to form a single dual port SRAM block being deeper than one of the plurality of megacells.

25. The method of claim 24, wherein cascading comprises selectively coupling data buses of the second one or more routing resources.

26. The method of claim 17, further comprising cascading two or more of the plurality of megacells to form a single dual port SRAM block being wider than one of the plurality of megacells.

27. The method of claim 26, wherein cascading comprises selectively coupling address buses of the second one or more routing resources.

28. The method of claim 17, further comprising cascading four or more of the plurality of megacells to form a single dual port SRAM block being deeper and wider than one of the plurality of megacells.

29. The method of claim 28, wherein cascading comprises selectively coupling data buses and address buses of the second one or more routing resources.