Differential output circuit with reduced differential output variation

• US 7,382,160 B2
• Filed: 05/08/2007
• Issued: 06/03/2008
• Est. Priority Date: 04/14/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nagano, Hideo, Aoyagi, Keisuke, Suzuki, Masao
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/797,807
• Publication Number:
  US 20070210868A1
• Time in Patent Office: 392 Days
• Field of Search: None
• US Class Current: 326/86
• CPC Class Codes: H03F 2203/45396 the AAC comprising one or more switches
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062

Abstract

In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.

Claims

1. An interface circuit comprising a differential output circuit outputting a differential output signal from first and second output terminals and an external circuit receiving said output signal from said differential output circuit, wherein

said output circuit comprises first and second MOS transistors, first and second amplifiers, first and second loads and first, second, third, fourth and fifth switches, and

said external circuit comprises an external load connected between said first and second output terminals, wherein:

said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said second and fourth switches;

said first amplifier has a negative terminal connected to a first fixed potential, and a positive terminal to said first and second loads;

said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said first and third switches;

said second amplifier has a positive terminal connected to a second fixed potential, and a negative terminal to said fifth switch at a first terminal;

said first and second switches are connected to a first node connected to said fifth switch at said first output terminal and to said first load;

said third and fourth switches are connected to a second node connected to said fifth switch at said second output terminal and to said second load;

said fifth switch has said first output terminal connected to said first terminal when said second and third switches turn on; and

said fifth switch has said second output terminal connected to said first terminal when said first and fourth switches turn on.

2. An interface circuit comprising a differential output circuit outputting a differential output signal from first and second output terminals and an external circuit receiving said output signal from said differential output circuit, wherein

said output circuit comprises first and second MOS transistors, first and second amplifiers, first and second loads and first, second, third, fourth and fifth switches, and

said external circuit comprises an external load connected between said first and second output terminals, wherein:

said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said second and fourth switches;

said first amplifier has a negative terminal connected to a first fixed potential, and a positive terminal to said first and second loads;

said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said first and third switches;

said second amplifier has a positive terminal connected to said fifth switch at a first terminal, and a negative terminal to a second fixed potential;

said first and second switches are connected to a first node connected to said fifth switch at said first output terminal and to said first load;

said third and fourth switches are connected to a second node connected to said fifth switch at said second output terminal and to said second load;

said fifth switch has said first output terminal connected to said first terminal when said first and fourth switches turn on; and

said fifth switch has said second output terminal connected to said first terminal when said second and third switches turn on.

3. An interface circuit comprising a differential output circuit outputting a differential output signal from first and second output terminals and an external circuit receiving said output signal from said differential output circuit, wherein

said output circuit comprises first and second MOS transistors, first and second amplifiers, first and second loads and first, second, third, fourth and fifth switches, and

said external circuit comprises an external load connected between said first and second output terminals, wherein:

said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said first and third switches;

said first amplifier has a positive terminal connected to said first and second loads, and a negative terminal to a first fixed potential;

said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said second and fourth switches;

said second amplifier has a positive terminal connected to said fifth switch at a first terminal, and a negative terminal to a second fixed potential;

said first and second switches are connected to a first node connected to said fifth switch at said first output terminal and to said first load;

said third and fourth switches are connected to a second node connected to said fifth switch at said second output terminal and to said second load;

said fifth switch has said first output terminal connected to said first terminal when said second and third switches turn on; and

said fifth switch has said second output terminal connected to said first terminal when said first and fourth switches turn on.

4. An interface circuit comprising a differential output circuit outputting a differential output signal from first and second output terminals and an external circuit receiving said output signal from said differential output circuit, wherein

said output circuit comprises first and second MOS transistors, first and second amplifiers, first and second loads and first, second, third, fourth and fifth switches, and

said external circuit comprises an external load connected between said first and second output terminals, wherein:

said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said first and third switches;

said first amplifier has a positive terminal connected to said first and second loads, and a negative terminal to a first fixed potential;

said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said second and fourth switches;

said second amplifier has a positive terminal connected to a second fixed potential, and a negative terminal to said fifth switch at a first terminal;

said first and second switches are connected to a first node connected to said fifth switch at said first output terminal and to said first load;

said third and fourth switches are connected to a second node connected to said fifth switch at said second output terminal and to said second load;

said fifth switch has said first output terminal connected to said first terminal when said first and fourth switches turn on; and

said fifth switch has said second output terminal connected to said first terminal when said second and third switches turn on.