Monolithic inductor for an RF integrated circuit

• US 7,382,222 B1
• Filed: 12/29/2006
• Issued: 06/03/2008
• Est. Priority Date: 12/29/2006
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Manetakis, Konstantinos
• Primary Examiner(s): NGUYEN, TUYEN T
• Application Number:
  US11/617,969
• Time in Patent Office: 522 Days
• Field of Search: 336/65, 336/83, 336/200, 336206-208, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate

Abstract

An integrated high frequency inductor is disclosed that includes first and second conductor loops. The first conductor loop is fabricated in a conductive layer of a semiconductor substrate and having a first substantially constant width. The second conductor loop is fabricated in the conductive layer and within the boundary of the first conductor loop and having a second substantially constant width less than the first substantially constant width, and the outer perimeter of the second conductor loop separated from the inner perimeter of the first conductor loop by a substantially constant gap. A first conductor bridge connects a first end of the first conductor loop to a first end of the second conductor loop. A second conductor bridge is provided for connecting a fourth end of the first conductor loop to a second end of the second conductor loop, the first and second conductor bridges operable to form a single conductive loop between the first and second ends of the first conductor loop, the single conductive loop comprised of the first conductor loop, the second conductor loop, the first conductor bridge and the second conductor bridge.

Claims

1. An integrated high frequency inductor, comprising:

a first conductor loop fabricated in a conductive layer of a semiconductor substrate and having a first substantially constant width, said first conductor loop having a first break therein to form first and second ends and a second break therein to form third and fourth ends, said first and second ends able to be interfaced to external nodes comprising two opposite ends of the inductor;

a second conductor loop fabricated in said conductive layer and within the boundary of said first conductor loop and having a second substantially constant width less than said first substantially constant width, and the outer perimeter of said second conductor loop separated from the inner perimeter of said first conductor loop by a substantially constant gap, said second conductor loop having a first break therein to form first and second ends;

a first conductor bridge for connecting the first end of said first conductor loop to the first end of said second conductor loop; and

a second conductor bridge for connecting said fourth end of said first conductor loop to the second end of said second conductor loop, said first and second conductor bridges operable to form a single conductive loop between said first and second ends of said first conductor loop to carry current in a first direction within said first conductor loop and said second conductor loop such that current flowing through one of said first or second conductor loops is parallel in direction to the substantially same current flowing through the other thereof, said single conductive loop comprised of said first conductor loop, said second conductor loop, said first conductor bridge and said second conductor bridge, and wherein said first and second substantially constant widths and the length of said first conductor loop and said conductor loop are optimized for inductance value and quality factor.

2. The inductor of claim 1 wherein said first and second conductor loops are fabricated of metal.

3. The inductor of claim 1 wherein said first conductor bridge is formed in the same conductive layer as said first conductor loop and said second conductor loop.

4. The inductor of claim 3, wherein said second conductive bridge is formed in a conductor layer that is disposed adjacent said conductive layer in which said first and second conductor loops are formed and separated therefrom by a dielectric layer, with the ends of said second conductor bridge connected through said dielectric layer to said fourth end of said first conductor loop and said second conductor loop.

5. The inductor of claim 1 wherein said first conductor loop and said second conductor loop have rectangular configurations.

6. The inductor of claim 1 wherein said first conductor loop and said second conductor loops have a substantially square configuration.

7. The inductor of claim 1, wherein said first width of said first substantially constant width and second substantially constant width are related such that said second substantially constant width is between twenty-five percent (25%) and seventy-five percent (75%) of said first substantially constant width.

8. The inductor of claim 7, wherein said second substantially constant width has a width that is approximately fifty percent (50%) of said first substantially constant width.