High intrascene dynamic range NTSC and PAL imager

• US 7,382,407 B2
• Filed: 08/29/2002
• Issued: 06/03/2008
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Barna, Sandor L., Subbotin, Igor, Kaplinsky, Michael, Cho, Kwang-Bo, Slayton, Gary E.
• Primary Examiner(s): Ye; Lin
• Assistant Examiner(s): Yoder, III; Chriss S
• Application Number:
  US10/230,205
• Publication Number:
  US 20040041927A1
• Time in Patent Office: 2,105 Days
• Field of Search: 348/254, 348/296, 348/304, 348/305, 348/308, 348/257, 348/295, 348/395, 348/396, 257/291, 257/292
• US Class Current: 348/296
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

The invention provides a new method and apparatus for NTSC and PAL image sensors which employs fusion of adjacent row pixel charge samples to generate image data for a row. A variety of fusion schemes are possible for fusing the pixel signals from the adjacent rows. The rows of pixels are scanned so that each scan takes an odd row signal sample and, in some cases, an adjacent even row signal sample when specified conditions are met. One sampled row of the two adjacent rows integrate an image with a first integration period while the other adjacent row integrates an image with a second integration period.

Claims

1. A pixel imager comprising:

a first pixel circuit in a first pixel row for outputting at least a first pixel image signal accumulated during a first integration period;

a second pixel circuit in a pixel row different from the first pixel row for outputting at least a second pixel image signal accumulated during a second integration period which is shorter than said first integration period; and

a sample and hold circuit for selectively acquiring at least one of said first and second pixel image signals and for outputting a pixel output signal which is based on at least one of (1) an average of said first and second pixel signals and (2) a selection of one of said first and second pixel image signals in accordance with a value of said first pixel image signal.

2. A pixel readout circuit comprising:

a sample and hold circuit for sampling a first pixel signal from a first selected row of pixels having a first integration period, said sample and hold circuit being selectively operable to sample a second pixel signal from a second adjacent selected row of pixels, which has a second integration period shorter than said first integration period;

a switching circuit coupled to said sample and hold circuit for controlling sampling of said first and second pixel signals;

a comparator for determining if a sampled first pixel signal exceeds a threshold signal value;

said switching circuit operating said sample and hold circuit to sample said first pixel signal and providing said first pixel signal as an output signal if said comparator determines that said threshold is exceeded by said sampled first pixel signal, and operating said sample and hold circuit to sample and hold said second pixel signal and provide said second pixel signal as an output when said threshold is not exceeded.

3. A pixel readout circuit of claim 2 wherein a pixel array comprises a plurality of sets of said first row of pixels with a first integration period and said second adjacent row of pixels with a shorter integration period.

4. A pixel readout circuit of claim 2 wherein said switching circuit is configured to control said sampling of said pixel rows in a pixel array such that said sampling begins at a first row on one end of the pixel array and is repeated for each of a said first row and said second adjacent row set, said sampling proceeding in the direction of the opposite end of said pixel array where said first row is located.

5. A pixel readout circuit of claim 2 further comprising a digital image processing unit, said unit comprising gamma table lookup for conversion of output signal from one display output signal to another.

6. A pixel readout circuit of claim 2 further comprising a flag storage circuit which stores a flag, wherein said flag is set to a first value if said comparator determines said threshold is exceeded or said flag is set to a second value if said comparator determines said threshold is not exceeded said flag being used to control said sample and hold circuit.

7. A pixel readout circuit of claim 6 further comprising an amplifier for output of said sample and hold circuit and a digital image processing circuit coupled to said amplifier, wherein said digital image processing circuit performs additional image processing based on the status of said flag.

8. A pixel readout circuit of claim 2 wherein said threshold value is a signal which corresponds to a pixel saturation signal.

9. A pixel readout circuit comprising:

a sample and hold circuit for sampling a pixel signal from selected row of pixels;

an amplifier for amplifying an output of said sample and hold circuit; and

a switching circuit coupled to said sample and hold circuit for controlling sampling of signals from a selected row of pixels, said switching circuit operating to sample and hold a first and second pixel signal from a pixel row having a first integration period and a third and fourth pixel signal from an adjacent pixel row having a second integration period, different from said first integration period;

wherein said sample and hold circuit averages said first and third pixel signals as well as said second and fourth pixel signals and provides an averaged first and second pixel signal to said amplifier.

10. A pixel readout circuit of claim 9 wherein said first integration period is relatively long with respect to said second integration period and said first pixel signal is a pixel signal remaining after said first integration period has elapsed.

11. A pixel readout circuit of claim 9 wherein said first pixel signal is a pixel signal remaining after said first integration period and said second pixel signal is a reset pixel signal.

12. A pixel readout circuit of claim 9 wherein said switching circuit is configured to control said sampling of said pixel rows in a pixel array such that said sampling begins at a first row on one end of the pixel array and is repeated fort each of a said first row and said second adjacent row set, said sampling proceeding in the direction of the opposite end of said pixel array where said first row is located.

13. A pixel readout circuit comprising:

a sample and hold circuit for sampling a pixel signal from a selected row of pixels;

an amplifier for amplifying an output of said sample and hold circuit;

a switching circuit coupled to said sample and hold circuit for controlling sampling of signals from selected row of pixels;

a comparator for determining if a selected pixel signal exceeds a threshold signal value;

said switching circuit operating to sample and hold a first and second pixel signal from a pixel row having a first integration period and a third and fourth pixel signal from a pixel row different from the first pixel row, having a second integration period which is shorter than said first integration period;

wherein said switching circuit operates said sample and hold circuit to provide said first and third signal to said amplifier if said comparator determines that said threshold is exceeded by said first pixel signal, and operating said sample and hold circuit to combine said first and third pixels signals together resulting in a first averaged pixel signal and also combine said second and fourth pixel signals together resulting in a second averaged pixel signal, and providing said first and second averaged pixel signal to said amplifier when said threshold is not exceeded by said first pixel signal.

14. A pixel readout circuit of claim 13 wherein said first and second rows are adjacent.

15. A pixel readout circuit of claim 13 wherein said second and fourth signals are a pixel reset signal.

16. A pixel readout circuit of claim 13 further comprising a flag storage circuit coupled to said comparator which stores a flag, wherein said flag is set to a first value if said comparator determines said threshold is not exceeded or said flag is set to a second value if said comparator determines said threshold is exceeded, said flag enables said combining of said signals when said flag is set to said second value.

17. A pixel readout circuit of claim 16 further comprising a digital image processing circuit coupled to said amplifier and said storage circuit, wherein said digital image processing circuit performs additional image processing based on said flag.

18. A pixel readout circuit of claim 13 wherein said threshold value is a signal which corresponds to a pixel saturation signal.

19. A pixel readout of claim 13 wherein said switching circuit is configured to commence said sampling of a said first row with a first integration period that is located on an end of the pixel array and wherein said sampling of a pixel row with a first integration period and a pixel row with a second integration period is progressively repeated moving away from the end of the pixel array where said first row is located.

20. A method of reading out a pixel array comprising:

outputting a first pixel image signal accumulated during a first integration period from a first pixel circuit in a first pixel row;

outputting a second pixel image signal accumulated during a second integration period which is shorter than said first integration period from a pixel circuit in a pixel row different from the first pixel row;

selectively sampling and holding at least one of said first and second pixel signals; and

outputting a pixel output signal which is based on a selection of one of said first and second pixel image signals, in accordance with a value of said first pixel image signal.

21. A method of claim 20 wherein said second pixel is adjacent to said first pixel row.

22. A method of claim 20 wherein said average of first and second pixel signals further comprises a pixel reset signal.

23. A method of performing a progressive scan readout of a pixel array comprising:

selecting a pixel in a first row within a pixel array with a first integration time;

sampling and holding a pixel signal from said pixel in said first row within a sample and hold circuit;

resetting said pixel with a reset signal;

sampling and holding said reset signal and a second pixel signal;

comparing said first pixel signal with a threshold signal and determining said first pixel signal exceeds said threshold signal;

outputting said first pixel signal and second pixel signal to an amplifier circuit if said comparison determines said first signal exceeds said threshold signal; and

if said determination determines said first pixel signal does not exceed said threshold signal, discharging said first and second pixel signals held in said sample and hold circuit, selecting a pixel within a second adjacent pixel row in said pixel array, then sampling and holding a third and fourth pixel signal from said selected pixel, said third and fourth pixel signals are output into an amplifier after being sampled and held.

24. A method as in claim 23 wherein said threshold signal is a voltage signal representing a saturation voltage in a pixel in said pixel array.

25. A method as in claim 23 wherein said first integration time commences first, then said second integration time commences with both first and second integration times terminating simultaneously.

26. A method of performing a progressive read-out of pixels in a CMOS pixel array comprising:

sampling a first pixel signal from a pixel in a pixel row having a first integration time;

charging said first pixel having a first integration time with a pixel reset signal and sampling said pixel reset signal as a second pixel signal;

sampling a third pixel signal from a pixel in a pixel row having a second integration time, wherein said second pixel row is adjacent to said pixel row having a first integration time;

charging said pixel having a second integration time, different from said first integration time, with said pixel reset signal and sampling said pixel reset signal as a fourth pixel signal;

combining said first and second pixel signals to produce a first averaged pixel signal;

combining said third and fourth pixel signals to produce a second averaged pixel signal;

outputting said first and second averaged signals; and

repeating said progressive read-out if another pixel row having a first integration time and an adjacent second pixel row having a second integration time has unsampled signals from a current said first and second integration period.

27. A method as in claim 26 wherein said first integration time commences first, then said second integration time commences with both first and second integration times terminating simultaneously.

28. A method for performing progressive readout of a pixel array comprising:

performing integration operations with a plurality of pixels within a pixel array, said pixel array comprised of pairs of an odd and adjacent even pixel row, said odd pixel rows having a first integration time and said even pixel rows having a second integration time different from said first integration time;

sampling an d holding a first pixel signal from a pixel in an odd pixel row in a sample and hold circuit;

charging said pixel with a pixel reset signal;

sampling and holding a second pixel signal from said pixel in said sample and hold circuit;

sampling and holding a third pixel signal from a pixel in an even pixel row in a sample and hold circuit;

charging said pixel with a pixel reset signal;

sampling and holding a fourth pixel signal from said pixel in said sample and hold circuit;

comparing said first pixel signal with a threshold signal, wherein said comparison is used to determine if said first signal exceeds a threshold signal;

outputting said first and second pixel signals to an amplifier if said first signals exceeds said threshold voltage;

if said first signal does not exceed said threshold signal, combining said first and third pixel signals to produce a first averaged pixel signal and combining said second and fourth pixel signals to produce a second averaged pixel signal, said first and second signals outputted to an amplifier as differential inputs to said amplifier; and

repeating said method for performing a progressive readout until each pair of an odd pixel row and adjacent even pixel row in said pixel array are processed.

29. A method as in claim 28 wherein said integration time is shorter than said first integration time.

30. A method as in claim 28 wherein said first integration time commences first, then said second integration time commences with both first and second integration times terminating simultaneously.

31. A method as in claim 28 wherein said threshold signal is a voltage signal representing a saturation voltage in a pixel in said pixel array.

32. A method of operating a pixel array comprising:

sampling a first pixel signal from a pixel in a first pixel row, said first pixel signal having a first integration period;

sampling a first pixel reset signal from said pixel in said first pixel row;

selectively sampling a second pixel signal from a pixel in a pixel row different from the first pixel row, said second pixel signal having a second integration period and wherein said pixel row different from the first pixel row is adjacent to said first pixel row;

selectively sampling a second pixel reset signal from said pixel in said pixel row different from the first pixel row; and

selectively using a combination of pixel signals to produce an output signal, said signals comprising said first sampled pixel signal and said first pixel reset signals as well as said second sampled pixel signal and said second pixel reset signal.

33. A method of claim 32 wherein “

selectively using”

comprises combining the first and second sampled and held signals based on a comparison of one of said sampled signals to a predetermined signal.

34. A method of claim 32 wherein “

selectively using”

comprises comparing said first pixel signal with a threshold signal and selecting for output said first or second pixel signal based on said comparison.

35. A method of claim 34 wherein said first pixel signal is selected for output if said first pixel signal is greater than said threshold signal.

36. A method of claim 35 wherein said threshold signal is a saturation voltage level for a pixel within said pixel array.

37. A method of claim 34 wherein said second pixel is selected for output if said first pixel signal is less than said threshold signal.

38. A method of claim 34 wherein said threshold signal is a saturation voltage level for a pixel within said pixel array.

39. A method of operating a pixel array comprising:

sampling a first pixel signal from a first pixel row from said array, said first pixel signal having a first integration period;

selectively sampling a second pixel signal from a pixel row different from the first pixel row adjacent to said first pixel row, said second pixel signal having a second integration period different from the first integration period; and

selectively using said pixel signals to produce an output signal.

40. A method of claim 39 wherein “

selectively sampling”

comprises sampling said second pixel signal if said first pixel signal exceeds a predetermined signal.

41. A method of claim 40 wherein said predetermined signal is a voltage value corresponding to a pixel saturation voltage from said pixel array.

42. A method of claim 39 wherein “

selectively using”

comprises combining the first pixel signal with a pixel reset signal and said second pixel signal with another pixel reset signal to produce a signal output.