NAND flash memory and blank page search method therefor

• US 7,382,652 B2
• Filed: 11/30/2006
• Issued: 06/03/2008
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Lin, Chin Hsi, Shiga, Hitoshi, Wang, Chih-Hung
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/564,887
• Publication Number:
  US 20070097750A1
• Time in Patent Office: 551 Days
• Field of Search: 365/185.17, 365/185.11, 365/185.33
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Claims

1. A blank page search method for a semiconductor memory device, comprising:

setting a selection word line voltage to a first level and detecting at once whether all data in two pages are in an erase state; and

when it is detected at once that not all the data are in the erase state, setting the selection word line voltage to a second level and detecting at once whether all data in one of the two pages are in the erase state.

2. The method according to claim 1, wherein page addresses in a block as an erase unit are sequentially divided into ½

and read-accessed to search for a page in which all data are in the erase state.

3. The method according to claim 2, wherein the block is a group of NAND strings which share a word line.

4. The method according to claim 1, wherein the semiconductor memory device is nonvolatile.

5. The method according to claim 1, wherein a memory cell array of the semiconductor memory device includes a string in which a plurality of adjacent memory cells are connected in series.