Dynamically adaptable semiconductor parametric testing

• US 7,383,147 B2
• Filed: 01/30/2006
• Issued: 06/03/2008
• Est. Priority Date: 04/25/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Blunn, Robert G., Velichko, Sergey A., Dorough, Michael J.
• Primary Examiner(s): Barlow; John
• Assistant Examiner(s): Washburn; Douglas N
• Application Number:
  US11/342,425
• Publication Number:
  US 20060125509A1
• Time in Patent Office: 855 Days
• Field of Search: 324/512, 324/523, 324/527, 438/6, 438/11, 438/12, 438/13, 702/117, 702/118
• US Class Current: 702/118
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a wafer, the tests to perform at each location, and the measured results of each test. A parametric test system may perform the test at the associated location on the wafer. If the statistical threshold is exceeded or the selected criteria is met, the current map may be abandoned in favor of a different map.

Claims

1. A method of parametric testing of semiconductor wafers, comprising:

loading a first semiconductor wafer onto a probing machine having a probe head;

loading a first map selected from a plurality of map sets, the first map operable for directing a first sequence of prober movements to perform parametric tests at each location in the first map;

loading a second map selected from the plurality of map sets, the second map operable for directing a second sequence of prober movements to perform parametric tests at each location in the first map;

loading a parametric test defect threshold determined from historical data of testing other wafers;

moving the probe head in the first sequence of prober movements specified in the first map;

probing test pins with the probe head to perform tests on the wafer at each location in the first probing sequence;

recording test results of each test at each respective location;

halting the prober when the test results indicate the defect threshold has been exceeded;

switching from the first map to the second map;

moving the probe head in the second sequence of prober movements specified in the second map; and

recording test results of each test at each respective location.

2. The method of claim 1, wherein the halting occurs prior to completion of the first probing sequence.

3. The method of claim 1, wherein the halting comprises removing electrical test stimuli from the wafer prior to the switching between the maps.

4. The method of claim 1, wherein the switching comprises switching from the first map being a composite wafer map to the second map being an aggregate wafer map.

5. The method of claim 1, wherein the parametric test defect threshold includes a badsite threshold, and further comprising determining the badsite threshold based on a total number of bad sites for the first map and a total number of sites on the first map.

6. The method of claim 1, wherein the parametric test defect threshold includes a badwafer threshold, and further comprising determining the badwafer threshold based on a total number of bad wafers in a lot run and a total number of wafers in the lot run.

7. The method of claim 1, wherein one of the first map and the second map includes a map operable for directing a sequence of prober movements in a serpentine-like prober-movement pattern.

8. The method of claim 1, wherein one of the first map and the second map includes a map operable for directing a sequence of prober movements in a row-by-row prober-movement pattern.

9. The method of claim 1, wherein one of the first map and the second map includes a map operable for directing a sequence of prober movements in a user-defined prober-movement pattern.

10. The method of claim 9, further comprising tailoring the user-defined prober-movement pattern to identify specific process-related problems.

11. A method of parametric testing of semiconductor wafers, comprising:

loading a first semiconductor wafer onto a probing machine having a probe head;

loading a plurality of maps each operable for directing a sequence of prober movements to perform parametric tests at each location in that map;

loading a statistically determined defect threshold;

moving the probe head in a first sequence of prober movements specified in a first map of the plurality of maps;

probing test pins with the probe head to perform tests on the wafer at each location in the first sequence of prober movements;

recording test results of each test at each respective location;

halting the prober when the test results indicate the defect threshold has been exceeded;

switching from the first map to a second map of the plurality of maps, the second map different from the first map;

moving the probe head in a second sequence of prober movements specified in the second map; and

recording test results of each test at each respective location.

12. The method of claim 11, wherein the halting occurs prior to completion of the first sequence of prober movements.

13. The method of claim 12, wherein the halting comprises removing electrical test stimuli from the wafer prior to the switching between the maps.

14. The method of claim 13, wherein the switching comprises switching from the first map being a composite wafer map to the second map being an aggregate wafer map.

15. The method of claim 11, wherein the statistically determined defect threshold includes a badsite threshold, and further comprising determining the badsite threshold based on a total number of bad sites for the first map and a total number of sites on the first map.

16. The method of claim 11, wherein the statistically determined defect threshold includes a badwafer threshold, and further comprising determining the badwafer threshold based on a total number of bad wafers in a lot run and a total number of wafers in the lot run.

17. The method of claim 11, wherein the plurality of maps includes a map operable for directing a sequence of prober movements in a serpentine-like prober-movement pattern.

18. The method of claim 11, wherein the plurality of maps includes a map operable for directing a sequence of prober movements in a row-by-row prober-movement pattern.

19. The method of claim 11, wherein the plurality of maps includes a map operable for directing a sequence of prober movements in a user-defined prober-movement pattern.

20. The method of claim 19, further comprising tailoring the user-defined prober-movement pattern to identify specific process-related problems.