Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage

• US 7,383,362 B2
• Filed: 08/28/2006
• Issued: 06/03/2008
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, I-Kang
• Primary Examiner(s): Chen; Alan S
• Application Number:
  US11/309,594
• Publication Number:
  US 20070079043A1
• Time in Patent Office: 645 Days
• Field of Search: 710/8, 710/20, 710/22, 710/62, 710/72, 713/1, 713/2
• US Class Current: 710/22
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Claims

1. A Multi-Media Card (MMC) single-chip flash device comprising:

a MMC flash microcontroller having a central processing unit (CPU) for executing instructions and a random-access memory (RAM) for storing instructions for execution by the CPU;

a bus transceiver in the MMC flash microcontroller for receiving MMC commands from a host over a host MMC bus;

a flash-memory controller in the MMC flash microcontroller;

flash mass storage blocks, coupled to the flash-memory controller, for storing non-volatile data for the host, the data in the flash mass storage blocks being block-addressable and not randomly-addressable; and

a flash bus having parallel data lines for transferring data from the flash-memory controller to the flash mass storage blocks, the flash bus also carrying a command to the flash mass storage blocks over the parallel data lines and also carrying a flash address over the parallel data lines;

wherein a block of data in the flash mass storage blocks is addressable by the flash-memory controller sending the command and a physical address over the parallel data lines, the command and the physical address being used to transfer the block of data over the parallel data lines as a plurality of data words transferred in a plurality of bus cycles;

whereby the MMC flash microcontroller is integrated with the flash mass storage blocks that are block-addressable.

2. The MMC single-chip flash device of claim 1 wherein instructions are stored only in the RAM for execution, wherein the CPU executes instructions stored only in the RAM;

wherein the instructions are transferred from a copy of the instructions in the flash mass storage blocks to the RAM during a power-on sequence before the CPU;

whereby instructions are transferred from the flash mass storage blocks to the RAM for execution by the CPU.

3. The MMC single-chip flash device of claim 2 wherein the MMC flash microcontroller does not contain a read-only memory (ROM) for storing instructions that is directly addressable by the CPU.

4. The MMC single-chip flash device of claim 2 wherein the flash mass storage blocks output instructions stored in a first page during the power-up sequence before the command or the physical address have been sent over the parallel data lines to the flash mass storage blocks,

whereby the flash mass storage blocks automatically read instructions stored in the first page during the power-on sequence.

5. The MMC single-chip flash device of claim 4 further comprising:

a direct-memory access (DMA) engine for transferring data among the flash-memory controller, the RAM, and the bus transceiver, the DMA engine being programmed for a transfer.

6. The MMC single-chip flash device of claim 5 further comprising:

a flash programming engine, coupled to the flash-memory controller, for programming the DMA engine to transfer instructions from the first page of the flash mass storage blocks to the RAM during an initial portion of the power-on sequence.

7. The MMC single-chip flash device of claim 6 wherein the instructions transferred from the first page of the flash mass storage blocks comprise a boot loader program;

wherein the CPU is brought out of reset and begins executing instructions from the RAM once the boot loader program has been transferred to the RAM by the DMA engine;

wherein the CPU executes the boot loader program loaded into the RAM from the flash mass storage blocks.

8. The MMC single-chip flash device of claim 7 wherein the boot loader program contains instructions for the CPU to transfer a control program from the flash mass storage blocks to the RAM, the control program being executed by the CPU upon completion of transfer.

9. The MMC single-chip flash device of claim 2 wherein the MMC single-chip flash device has only eight data pins, the eight data pins being clocked data lines for transferring MMC data over the host MMC bus.

10. The MMC single-chip flash device of claim 9 wherein the MMC single-chip flash device is in a package having twenty or fewer external pins.

11. The MMC single-chip flash device of claim 2 wherein the physical address is a partial address of a page of data in the flash mass storage blocks, the partial address having fewer address bits than a full word address that uniquely identifies a word of data in the flash mass storage blocks that can be transferred over the parallel data lines in a single bus cycle.

12. The MMC single-chip flash device of claim 2 further comprising:

an internal bus in the MMC flash microcontroller, the internal bus connecting to the CPU, to the RAM, to a buffer for the bus transceiver, and to the flash-memory controller;

wherein the instructions executed by the CPU are transferred from the flash mass storage blocks over the flash bus to the flash-memory controller and then to the internal bus for storage by the RAM.

13. A single-chip flash device comprising:

a clocked-data interface to a host bus that connects to a host;

a bus transceiver for detecting and processing commands sent over the host bus;

a buffer for storing data sent over the host bus;

an internal bus coupled to the buffer;

a random-access memory (RAM) for storing instructions for execution, the RAM on the internal bus;

a central processing unit, on the internal bus, the CPU accessing and executing instructions in the RAM;

a flash-memory controller, on the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to a flash bus;

flash mass storage blocks coupled to the flash-memory controller by the flash bus, and controlled by the flash-control signals;

a direct-memory access (DMA) engine, on the internal bus, for transferring data over the internal bus; and

a flash programming engine, activated by a reset, for initially programming the DMA engine to transfer an initial program of instructions from the flash mass storage blocks to the RAM before the CPU begins execution of instructions after the reset;

whereby the initial program of instructions is transferred from the flash mass storage blocks to the RAM before execution by the CPU begins, eliminating a need for a local read-only memory (ROM) for storing the initial program of instructions.

14. The single-chip flash device of claim 13 wherein the initial program of instructions is a boot-loader program that programs transfers a control program of instructors from the flash mass storage blocks to the RAM when the CPU begins execution of the boot-loader program after reset.

15. The single-chip flash device of claim 14 wherein data in the flash mass storage blocks are accessible by the flash-memory controller sending a request sequence over the flash bus, the request sequence including a command followed by a physical address;

wherein the data in the flash mass storage blocks is block-addressable while the RAM is randomly-addressable by the CPU.

16. The single-chip flash device of claim 15 wherein the flash mass storage blocks are initially readable after a reset before receiving a command and a physical address over the flash bus;

wherein the flash mass storage blocks send data in a first page over the flash bus after the reset and before receiving a command and a physical address over the flash bus.

17. The single-chip flash device of claim 13 wherein the host bus is a Multi-Media Card (MMC) bus having parallel data lines and a clock, or wherein the host bus is a Secure Digital (SD) bus having parallel data lines and a clock, or wherein the host bus is a Memory-Stick bus, a PCI Express bus, an IDE bus, or a Serial ATA (SATA) bus.

18. A flash drive comprising:

a Multi-Media Card/Secure Digital (MMC/SD) interface that connects to a host over a MMC/SD host bus;

a MMC/SD-flash microcontroller having a processor for executing instructions;

a main memory coupled to the processor for storing instructions for execution by the processor;

a flash-memory controller;

a flash mass storage block that is block-accessible by the processor through the flash-memory controller;

a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the MMC/SD interface, the main memory, the processor, and the flash-memory controller;

a flash programming engine for initially programming the DMA engine to read an initial program from a first page of the plurality of flash mass storage blocks and write the initial program to the main memory for execution by the processor.

19. The flash drive of claim 18 wherein the MMC/SD interface comprises:

a MMC/SD transceiver for receiving clocked data and commands from the host bus, and for driving data onto the host bus in response to a command;

MMC/SD operating registers for storing data and commands in a format specified by a Multi-Media Card (MMC) or Secure Digital (SD) specification; and

a command decoder and validator, coupled to the MMC/SD operating registers, for decoding and validating a command received over the host bus by the MMC/SD transceiver.