Apparatus and methods for storing data in a magnetic random access memory (MRAM)

• US 7,383,376 B2
• Filed: 09/27/2006
• Issued: 06/03/2008
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Swanson, Richard W.
• Primary Examiner(s): Sparks; Donald
• Assistant Examiner(s): DILLER, JESSE DAVID
• Application Number:
  US11/535,899
• Publication Number:
  US 20070030725A1
• Time in Patent Office: 615 Days
• Field of Search: 711/104
• US Class Current: 711/104
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments advantageously enhance the throughput of the MRAM and a related digital circuit, such as a computer system, which advantageously enhances the operating speed of the digital circuit.

Claims

1. A method of writing data in a memory, where the memory includes a magnetoresistive array of bits, where a bit from the magnetoresistive array stores one of a first state or a second state, where the second state is a logical inverse of the first state, the method comprising:

receiving an indication that data is to be written to a selected memory location comprising a plurality of data bits;

setting the data bits for the selected memory location to a first state based at least in part on receiving the indication that data is to be written;

receiving data to be written; and

writing the second state to the applicable data bits based on the received data, wherein setting the first state comprises activating a write current in a first direction for the data bits, and wherein writing the second state comprising activating a write current in a second direction opposite to the first direction for the applicable data bits.

2. A method of writing data in a memory, where the memory includes a magnetoresistive array of bits, where a bit from the magnetoresistive array stores one of a first state or a second state, where the second state is a logical inverse of the first state, the method comprising:

receiving an indication that data is to be written to a selected memory location comprising a plurality of data bits;

setting the data bits for the selected memory location to a first state based at least in part on receiving the indication that data is to be written, wherein writing the first state to the data bits is conducted in response to a first edge of a clock signal;

receiving data to be written, wherein reading the data to be written to the data bits is conducted a predetermined time after the first edge of the clock signal; and

writing the second state to the applicable data bits based on the received data.

3. The method as defined in claim 2, further comprising setting the data bits to the first state prior to receiving the data to be written.

4. The method as defined in claim 2, wherein reading the data to be written to the data bits is conducted at least partially in response to a second edge of the clock signal.

5. The method as defined in claim 2, wherein the method is embodied in a memory device.

6. The method as defined in claim 2, wherein the method is embodied in a controller.

7. The method as defined in claim 2, wherein the method is embodied in a removable memory card.

8. The method as defined in claim 2, wherein the method is embodied in a digital device.

9. An integrated circuit with a magnetic random access memory (MRAM) comprising:

a memory array of magnetoresistive cells, a magnetoresistive cell being configured to store one of a first state or a second state at a time; and

a control circuit configured to select a plurality of data bits for a memory write based at least in part on activation of a control signal for the memory write, to initiate a write operation to set the selected data bits to the first state, said initiation based at least in part on the activation of the control signal, said initiation occurring before the data to be written is received, wherein the control circuit is further configured to receive the data to be written and to write the second state to the applicable data bits according to the received data.

10. The integrated circuit as defined in claim 9, further comprising current drivers being configured to provide at least a write current in a first direction for writing the first state of data and to provide at least a write current in a second direction for selectively writing the second state of data.

11. The integrated circuit as defined in claim 9, further comprising sense amplifiers electrically coupled to the selected portion of the memory array, the sense amplifiers being configured to retrieve a stored state from the selected word.

12. The integrated circuit as defined in claim 9, wherein the read/write control circuit is further configured to receive a clock signal, wherein a first phase is initiated at least partially in response to one of a rising edge or a falling edge of the clock signal, and wherein a second phase is initiated at least partially in response to the other of the rising edge or the falling edge of the clock signal.

13. The integrated circuit as defined in claim 9, further comprising a multiplexer having a first input set to the first state, having a second input that receives a data input of the MRAM, having a control input, and having an output that is coupled to inputs of the current drivers, the multiplexer being configured to selectively transfer one of the first state on the first input or the data input on the second input to the output coupled to the inputs of the current drivers, the control input of the multiplexer being electrically coupled to the read/write control circuit so that the multiplexer provides the first state to the inputs of the current drivers in a first phase and provides the data input of the MRAM as the inputs of the current drivers in a second phase.

14. The integrated circuit as defined in claim 9, wherein the integrated circuit is a dedicated memory device.

15. The integrated circuit as defined in claim 9, wherein the integrated circuit is embodied in a digital audio player.