DRAM device and method of manufacturing the same

• US 7,384,841 B2
• Filed: 02/22/2006
• Issued: 06/10/2008
• Est. Priority Date: 03/05/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Hong-Sik, Yeo, In-Seok, Huo, Zong-Liang, Baik, Seung-Jae, Kim, Shi-Eun
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/358,060
• Publication Number:
  US 20060197131A1
• Time in Patent Office: 839 Days
• Field of Search: 438/238, 438/3, 438/257, 438/289, 438/381, 438/692, 438/733, 438/735, 438/736
• US Class Current: 438/238
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Claims

1. A method of manufacturing a dynamic random access memory (DRAM) device, comprising:

forming a multiple tunnel junction (MTJ) structure including conductive patterns and nonconductive patterns alternately stacked on each other, the nonconductive patterns having a band gap larger than a band gap of the conductive patterns;

forming a first insulation layer along a sidewall of the MTJ structure;

forming a gate electrode on the first insulation layer;

forming a word line electrically connected with the MTJ structure;

forming a bit line electrically connected with one of a top surface and a bottom surface of the MTJ structure; and

forming a capacitor electrically connected with one of a top surface and a bottom surface of the MTJ structure that is not connected with the bit line.

2. The method of claim 1, wherein forming the MTJ structure includes:

forming a first conductive layer on a substrate, the first conductive layer including polysilicon doped with first polarity type impurities;

alternately forming at least one nonconductive layer and at least one conductive layer on the first conductive layer until an n^th conductive layer is formed as a top portion of the MTJ structure, wherein n is an integer less than 4 and n conductive layers are sequentially formed on the substrate and (n−

1) nonconductive layers are sequentially interposed between adjacent conductive layers, and a first and the n^th conductive layer include polysilicon doped with first polarity type impurities, and residual conductive layers except the first and the n^th conductive layer include polysilicon doped with second polarity type impurities different from the first polarity type impurities; and

sequentially and alternately patterning the n conductive layers and the (n−

1) nonconductive layers.

3. A method of manufacturing a random dynamic access memory (DRAM) device, comprising:

forming a preliminary storage electrode on a substrate having a line shape extending in a first direction;

forming a preliminary multiple tunnel junction (MTJ) structure on the preliminary storage electrode, the MTJ structure including conductive layers and nonconductive layers alternately stacked on each other, the nonconductive layers having a band gap larger than a band gap of each conductive layers;

forming a conductive layer on the preliminary MTJ structure;

partially etching the conductive layer, the preliminary MTJ structure and the preliminary storage electrode in a second direction perpendicular to the first direction until a top surface of the substrate is exposed, thereby forming a bit line extending in the second direction and a plurality of MTJ structures and storage electrodes isolated from each other;

forming a first dielectric layer on a sidewall of the storage electrodes;

forming a plate electrode between adjacent storage electrodes so that a sidewall of the plate electrode contacts with the first dielectric layer;

forming an insulation layer on a top surface of the plate electrode, a sidewall of the MTJ structure and a top surface of the bit line; and

forming a word line on the insulation layer in the second direction, the word line facing the sidewall of the MTJ structure.

4. The method of claim 3, further comprising:

forming a second dielectric layer on the substrate prior to forming the preliminary storage electrode so a bottom surface of the plate electrode contacts the second dielectric layer and a sidewall of the plate electrode contacts the first dielectric layer.

5. The method of claim 3, wherein forming the preliminary MTJ structure includes:

forming a first conductive layer on the preliminary storage electrode, the first conductive layer comprising polysilicon doped with first polarity type impurities;

alternately forming at least one nonconductive layer and at least one conductive layer on the first conductive layer until an n^th conductive layer is formed at a top portion of the MTJ structure, wherein n is an integer less than 4 and n conductive layers are sequentially formed on the substrate and n−

1 nonconductive layers are sequentially interposed between adjacent conductive layers, a first and the n^th conductive layer include polysilicon doped with first polarity type impurities, and residual conductive layers except the first and the n^th conductive layers include polysilicon doped with second polarity type impurities that are different from the first polar type impurities; and

sequentially and alternately patterning the n conductive layers and the (n−

1) nonconductive layers.

6. The method of claim 3, further comprising forming a first hard mask pattern on the conductive layer.

7. The method of claim 3, further comprising forming a device isolation pattern between the preliminary storage electrode and the preliminary MTJ structure.

8. The method of claim 7, wherein forming the plate electrode includes:

forming a conductive layer on the substrate with a thickness sufficient to fill an opening defined by the device isolation pattern and the storage electrode; and

partially removing the conductive layer until a lower portion of the MTJ structure is exposed.

9. The method of claim 3, further comprising forming a second insulation layer on the plate electrode of which top surface is lower than a top surface of the storage electrode prior to forming the insulation layer.

10. The method of claim 9, wherein a top surface of the second insulation layer is coplanar with a top surface of the storage electrode.

11. The method of claim 3, wherein forming the word line includes:

forming a conductive layer on the insulation layer; and

partially etching the conductive layer to form a word line in the first direction, so the word line is perpendicular to the bit line and faces the sidewall of the MTJ structure at a lower portion thereof.